From patchwork Wed Sep 25 21:12:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 2944531 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C06A39F288 for ; Wed, 25 Sep 2013 21:14:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B9B0320583 for ; Wed, 25 Sep 2013 21:14:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B92D120565 for ; Wed, 25 Sep 2013 21:14:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755075Ab3IYVOX (ORCPT ); Wed, 25 Sep 2013 17:14:23 -0400 Received: from mail-vb0-f74.google.com ([209.85.212.74]:35074 "EHLO mail-vb0-f74.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755892Ab3IYVM5 (ORCPT ); Wed, 25 Sep 2013 17:12:57 -0400 Received: by mail-vb0-f74.google.com with SMTP id w16so35268vbf.3 for ; Wed, 25 Sep 2013 14:12:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2CmPFWsIcIUlNf4ZYBiJGkcV4oTbT5PZi9rbru2/7nE=; b=dv007aIsg0MBwOXZKiwftbgIh+k+cs7inaxQzSUlBPCdfC4/ay16VvSlvoI21rHOEV RvIeGVGi0Q8azYYzJUwH4WdFwe6kzxj6EjXJ0EG/O+0AJYMkDXPpqdEUN/97+Cnir4rK HSVql5WqpROXXjHfrVnPhChkUhFyqSmggZlri4kTOalpwmGsNIbec9GPNebGw0nPwJN7 IcK8VMQk3X7PHMmtDcUDwk27EbOawu/afDmviAO2Dbo7Y3WU6h3OLm+9G2ZFOaN6yBOX vf9jB2QOPkht8b9scG5WTQDbepCxhuMVJ4DNKQi+4hQFapvB+FnpzUTPv4Djugbwtv41 BtoA== X-Gm-Message-State: ALoCoQkZDGtmhzSImAlU4cdBjSEHkAebdecVlZ4VWktxWIZo8ocBqZILW9bSNRejg9pS0Sbl9g9X0VtDg7GXdvgTmtC09Z1iFrkMbIK59VwhHbY+qsGvZTawFXzVx1lNDO0thJrG3I5fGuM9IGDdM6R0q4Y8JZXpY0Egq+r78Bw0KPSo/Z+6oA5g9t4yAXJxKOgWEoIc62P0Fid8qZVrrvTRsmAMD3MmqA== X-Received: by 10.236.198.197 with SMTP id v45mr10792043yhn.26.1380143576069; Wed, 25 Sep 2013 14:12:56 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id d23si6097715yhn.2.1969.12.31.16.00.00 (version=TLSv1.1 cipher=AES128-SHA bits=128/128); Wed, 25 Sep 2013 14:12:56 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id C729D31C1DA; Wed, 25 Sep 2013 14:12:55 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id 859A3220862; Wed, 25 Sep 2013 14:12:55 -0700 (PDT) From: Andrew Bresticker To: Tomasz Figa , Sylwester Nawrocki , linux-samsung-soc@vger.kernel.org, Stephen Boyd Cc: Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Kukjin Kim , Russell King , Mike Turquette , Grant Likely , Sachin Kamat , Jiri Kosina , Rahul Sharma , Leela Krishna Amudala , Tushar Behera , Doug Anderson , Padmavathi Venna , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Bresticker Subject: [PATCH V4 2/6] clk: exynos-audss: allow input clocks to be specified in device tree Date: Wed, 25 Sep 2013 14:12:48 -0700 Message-Id: <1380143572-11741-2-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1380143572-11741-1-git-send-email-abrestic@chromium.org> References: <1380046016-5811-1-git-send-email-abrestic@chromium.org> <1380143572-11741-1-git-send-email-abrestic@chromium.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. Signed-off-by: Andrew Bresticker --- Changes since v1: - listed input clocks as required properties --- .../devicetree/bindings/clock/clk-exynos-audss.txt | 32 ++++++++++++++++++++-- drivers/clk/samsung/clk-exynos-audss.c | 25 +++++++++++++---- 2 files changed, 50 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index 75e2e19..85b9e28 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -14,6 +14,21 @@ Required Properties: - #clock-cells: should be 1. +- clocks: + - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" + is used if not specified. + - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" + is used if not specified. + - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not + specified. + - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if + not specified. + - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not + specified. + +- clock-names: Aliases for the above clocks. They should be "pll_ref", + "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively. + The following is the list of clocks generated by the controller. Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. Some of the clocks are available only on a particular @@ -35,15 +50,28 @@ sclk_i2s 7 pcm_bus 8 sclk_pcm 9 -Example 1: An example of a clock controller node is listed below. +Example 1: An example of a clock controller node using the default input + clock names is listed below. + +clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; +}; + +Example 2: An example of a clock controller node with the input clocks + specified. clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5250-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; + clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, + <&ext_i2s_clk>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk"; }; -Example 2: I2S controller node that consumes the clock generated by the clock +Example 3: I2S controller node that consumes the clock generated by the clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property. diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 742dabc..7cb10f2 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -34,10 +34,6 @@ static unsigned long reg_save[][2] = { {ASS_CLK_GATE, 0}, }; -/* list of all parent clock list */ -static const char *mout_audss_p[] = { "fin_pll", "fout_epll" }; -static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" }; - #ifdef CONFIG_PM_SLEEP static int exynos_audss_clk_suspend(void) { @@ -68,6 +64,10 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) { int i, ret = 0; struct resource *res; + const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; + const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; + const char *sclk_pcm_p = "sclk_pcm0"; + struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg_base = devm_ioremap_resource(&pdev->dev, res); @@ -85,11 +85,23 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) clk_data.clks = clk_table; clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; + pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); + pll_in = devm_clk_get(&pdev->dev, "pll_in"); + if (!IS_ERR(pll_ref)) + mout_audss_p[0] = __clk_get_name(pll_ref); + if (!IS_ERR(pll_in)) + mout_audss_p[1] = __clk_get_name(pll_in); clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); + cdclk = devm_clk_get(&pdev->dev, "cdclk"); + sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio"); + if (!IS_ERR(cdclk)) + mout_i2s_p[1] = __clk_get_name(cdclk); + if (!IS_ERR(sclk_audio)) + mout_i2s_p[2] = __clk_get_name(sclk_audio); clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), CLK_SET_RATE_NO_REPARENT, @@ -123,8 +135,11 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); + sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); + if (!IS_ERR(sclk_pcm_in)) + sclk_pcm_p = __clk_get_name(sclk_pcm_in); clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", - "div_pcm0", CLK_SET_RATE_PARENT, + sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); for (i = 0; i < clk_data.clk_num; i++) {