diff mbox

[1/3] clk: exynos5250: save/restore EPLL0 configuration

Message ID 1383905648-23733-1-git-send-email-sachin.kamat@linaro.org (mailing list archive)
State New, archived
Headers show

Commit Message

Sachin Kamat Nov. 8, 2013, 10:14 a.m. UTC
From: Andrew Bresticker <abrestic@chromium.org>

The EPLL configuration register needs to be saved across
suspend/resume.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
---
 drivers/clk/samsung/clk-exynos5250.c |    1 +
 1 file changed, 1 insertion(+)

Comments

Sachin Kamat Nov. 8, 2013, 10:21 a.m. UTC | #1
On 8 November 2013 15:44, Sachin Kamat <sachin.kamat@linaro.org> wrote:
> From: Andrew Bresticker <abrestic@chromium.org>
>
> The EPLL configuration register needs to be saved across
> suspend/resume.
>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
>  drivers/clk/samsung/clk-exynos5250.c |    1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index ee866e377c80..6767635dc895 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -143,6 +143,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
>         SRC_CPU,
>         DIV_CPU0,
>         SRC_CORE1,
> +       EPLL_CON0,
>         SRC_TOP0,
>         SRC_TOP2,
>         SRC_TOP3,
> --
> 1.7.9.5
>

Forgot to mention that this series is based on top of Tomasz Figa's
Exynos5250 cleanup series.
http://www.spinics.net/lists/arm-kernel/msg280039.html
Tomasz Figa Nov. 10, 2013, 5:01 p.m. UTC | #2
Hi Sachin, Andrew,

On Friday 08 of November 2013 15:44:06 Sachin Kamat wrote:
> From: Andrew Bresticker <abrestic@chromium.org>
> 
> The EPLL configuration register needs to be saved across
> suspend/resume.
> 
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
>  drivers/clk/samsung/clk-exynos5250.c |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index ee866e377c80..6767635dc895 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -143,6 +143,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
>  	SRC_CPU,
>  	DIV_CPU0,
>  	SRC_CORE1,
> +	EPLL_CON0,

What about EPLL_CON1 and EPLL_CON2? Also, have you considered register
restoration order?

Anyway, I believe it's not the correct way to restore PLL configuration.
See my Samsung PM consolidation series, especially patch [1] to see my
proposed way of handling this. (Beware of a bug that snuck into this patch
 - samsung_clk_save() is not being called for PLL registers.)

[1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/24078/focus=24087

Best regards,
Tomasz

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diff mbox

Patch

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index ee866e377c80..6767635dc895 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -143,6 +143,7 @@  static unsigned long exynos5250_clk_regs[] __initdata = {
 	SRC_CPU,
 	DIV_CPU0,
 	SRC_CORE1,
+	EPLL_CON0,
 	SRC_TOP0,
 	SRC_TOP2,
 	SRC_TOP3,