From patchwork Fri Dec 6 09:48:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Kumar K X-Patchwork-Id: 3294221 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id F07289F387 for ; Fri, 6 Dec 2013 09:49:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 25CFC204EC for ; Fri, 6 Dec 2013 09:49:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F266620462 for ; Fri, 6 Dec 2013 09:49:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757059Ab3LFJtJ (ORCPT ); Fri, 6 Dec 2013 04:49:09 -0500 Received: from mail-pb0-f46.google.com ([209.85.160.46]:56629 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755124Ab3LFJtH (ORCPT ); Fri, 6 Dec 2013 04:49:07 -0500 Received: by mail-pb0-f46.google.com with SMTP id md12so774717pbc.19 for ; Fri, 06 Dec 2013 01:49:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=tGgwTKGjFjxUyBSTKwEf1txRqMpT7X0assMWqE/nHzI=; b=qeiR+jRa37xLY8569dMHnwxFV8yRyX+f4Gh4zLuwov08crVmpvi0YRuLuxerzvgBDO WMMbsD7psx1zXSsdkhMW8ewc706whHNZ/CDXp5cV7tfZrKOktv1kuluYXcE0PdIsMamm Os7uF6r7S+izGLiH6jZjr/bmzUBXhoNMsS+4VM8dGrCLLz+5U0KAOLja1+i+PpwAxeOm r8a6NUA1LPLZitsJ7BxFrsDza5F1SqrlJEvNB4x93W1gGumlmpwNPWbRaLvk+xSReMZo Jp3+QbfOspEXCrMu7X3P0vGMKc2Crg6lrkO1EK8nh67mc2YKjCqEHfGcRdTUV7/EAfq8 QwGg== X-Received: by 10.68.212.10 with SMTP id ng10mr3123390pbc.158.1386323347361; Fri, 06 Dec 2013 01:49:07 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id yg3sm175098479pab.16.2013.12.06.01.49.03 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 06 Dec 2013 01:49:06 -0800 (PST) From: Arun Kumar K To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, cpufreq@vger.kernel.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, rjw@rjwysocki.net, viresh.kumar@linaro.org, tomasz.figa@gmail.com, arjun.kv@samsung.com, abrestic@chromium.org, arunkk.samsung@gmail.com Subject: [PATCH 1/3] ARM: EXYNOS: Add exynos5 CPU clock divider offsets Date: Fri, 6 Dec 2013 15:18:02 +0530 Message-Id: <1386323284-15646-2-git-send-email-arun.kk@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1386323284-15646-1-git-send-email-arun.kk@samsung.com> References: <1386323284-15646-1-git-send-email-arun.kk@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds the CPU clock divider shifts and masks for Exynos5 SoC. These defines will be used in cpufreq driver. Signed-off-by: Arjun.K.V Signed-off-by: Arun Kumar K --- arch/arm/mach-exynos/include/mach/regs-clock.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index d36ad76..d0186d3 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -347,6 +347,30 @@ #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) +/* CLK_DIV_CPU0 */ +#define EXYNOS5_CLKDIV_CPU0_CORE_SHIFT 0 +#define EXYNOS5_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_CORE_SHIFT) +#define EXYNOS5_CLKDIV_CPU0_CPUD_SHIFT 4 +#define EXYNOS5_CLKDIV_CPU0_CPUD_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_CPUD_SHIFT) +#define EXYNOS5_CLKDIV_CPU0_ACP_SHIFT 8 +#define EXYNOS5_CLKDIV_CPU0_ACP_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_ACP_SHIFT) +#define EXYNOS5_CLKDIV_CPU0_ATB_SHIFT 16 +#define EXYNOS5_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_ATB_SHIFT) +#define EXYNOS5_CLKDIV_CPU0_PCLKDBG_SHIFT 20 +#define EXYNOS5_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_PCLKDBG_SHIFT) +#define EXYNOS5_CLKDIV_CPU0_APLL_SHIFT 24 +#define EXYNOS5_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_APLL_SHIFT) +#define EXYNOS5_CLKDIV_CPU0_CORE2_SHIFT 28 +#define EXYNOS5_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS5_CLKDIV_CPU0_CORE2_SHIFT) + +/* CLK_DIV_CPU1 */ +#define EXYNOS5_CLKDIV_CPU1_COPY_SHIFT 0 +#define EXYNOS5_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS5_CLKDIV_CPU1_COPY_SHIFT) +#define EXYNOS5_CLKDIV_CPU1_HPM_SHIFT 4 +#define EXYNOS5_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS5_CLKDIV_CPU1_HPM_SHIFT) +#define EXYNOS5_CLKSRC_CPU_MUXCORE_SHIFT 16 +#define EXYNOS5_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS5_CLKSRC_CPU_MUXCORE_SHIFT) + #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) #define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)