From patchwork Fri Dec 6 15:56:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 3298801 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 007AEC0D4A for ; Fri, 6 Dec 2013 15:57:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A87DE20414 for ; Fri, 6 Dec 2013 15:57:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B95EE2052C for ; Fri, 6 Dec 2013 15:57:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757859Ab3LFP5h (ORCPT ); Fri, 6 Dec 2013 10:57:37 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:18478 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757802Ab3LFP5f (ORCPT ); Fri, 6 Dec 2013 10:57:35 -0500 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MXE00IJM6ZY25C0@mailout1.samsung.com>; Sat, 07 Dec 2013 00:57:34 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.125]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 43.71.16251.EE3F1A25; Sat, 07 Dec 2013 00:57:34 +0900 (KST) X-AuditID: cbfee691-b7fd26d000003f7b-2f-52a1f3ee0d65 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id FA.1C.17171.EE3F1A25; Sat, 07 Dec 2013 00:57:34 +0900 (KST) Received: from localhost.localdomain ([107.108.83.245]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MXE003WB6Z2JY10@mmp2.samsung.com>; Sat, 07 Dec 2013 00:57:34 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, thomas.ab@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, pankaj.dubey@samsung.com, yg1004.jang@samsung.com, arun.kk@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [PATCH 6/7] clk/samsung: add support for pll2650xx Date: Fri, 06 Dec 2013 21:26:30 +0530 Message-id: <1386345391-23482-7-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1386345391-23482-1-git-send-email-rahul.sharma@samsung.com> References: <1386345391-23482-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjkeLIzCtJLcpLzFFi42JZI2JSq/vu88Igg3ut8hYfT91mtZh/5Byr xfddX9gtehdcZbPY9Pgaq8WM8/uYLJ5OuMhmsWgrUGLhi3iLKYsOs1p0LGO0WLXrD6PFjpbV LA68Hjtn3WX3uHNtD5vH5iX1Hn1bVjF6fN4kF8AaxWWTkpqTWZZapG+XwJXx/eAkpoLXahXr jn5mbWDcpNDFyMEhIWAi8am/souRE8gUk7hwbz1bFyMXh5DAUkaJU/9mskIkgGoe/mWBSExn lJh46xsbSEJIoJ1JYu7cYBCbTUBXYvbBZ4wgQ0UEMiU2bskFqWcW+MsocWHrLnaQGmEBa4lt f7sZQWwWAVWJC2vPgdm8Ah4S93b9Y4I4SEFiziQbEJNTwFNi2YMAiE0eElse9rGDjJQQOMUu ceLIUlaIMQIS3yYfYoFolZXYdIAZ4mRJiYMrbrBMYBRewMiwilE0tSC5oDgpvchUrzgxt7g0 L10vOT93EyMwLk7/ezZxB+P9A9aHGJOBxk1klhJNzgfGVV5JvKGxmZGFqYmpsZG5pRlpwkri vOmPkoKEBNITS1KzU1MLUovii0pzUosPMTJxcEo1MLZ9OML70yHiRGj2lne3OecoMr3g4RHq 91C46qh74Iq371up2pAHPt6sihMeO2Q0B6WUSXeIPdXe3zhRrHvVrPk7HGe5xs/TVNV8K+Xv pHL8PH8D5zcf589zfvLu+aXWMn2604ON01Ycu3f2/aKuKdL7lnqXxkr27fF+nbZ0doBu4Kvz p7wyHJRYijMSDbWYi4oTARDgHSqhAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDIsWRmVeSWpSXmKPExsVy+t9jQd13nxcGGWy9K2Lx8dRtVov5R86x Wnzf9YXdonfBVTaLTY+vsVrMOL+PyeLphItsFou2AiUWvoi3mLLoMKtFxzJGi1W7/jBa7GhZ zeLA67Fz1l12jzvX9rB5bF5S79G3ZRWjx+dNcgGsUQ2MNhmpiSmpRQqpecn5KZl56bZK3sHx zvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlAJyoplCXmlAKFAhKLi5X07TBNCA1x07WAaYzQ 9Q0JgusxMkADCWsYM74fnMRU8FqtYt3Rz6wNjJsUuhg5OSQETCQ+PfzLAmGLSVy4t56ti5GL Q0hgOqPExFvf2EASQgLtTBJz5waD2GwCuhKzDz5j7GLk4BARyJTYuCUXpJ5Z4C+jxIWtu9hB aoQFrCW2/e1mBLFZBFQlLqw9B2bzCnhI3Nv1jwmkV0JAQWLOJBsQk1PAU2LZgwCITR4SWx72 sU9g5F3AyLCKUTS1ILmgOCk911CvODG3uDQvXS85P3cTIzjunkntYFzZYHGIUYCDUYmHl2PV giAh1sSy4srcQ4wSHMxKIrxH7iwMEuJNSaysSi3Kjy8qzUktPsSYDHTTRGYp0eR8YErIK4k3 NDYxNzU2tTSxMDGzJE1YSZz3QKt1oJBAemJJanZqakFqEcwWJg5OqQbGNX9CRP/XfkiZbZ0c yDmvYeVF3cN6z1Ofl3x4JnP3xZLb/P/7n/zf/nPpy2fWxlJrY+vCje8l8VwILzJj4bvP5Bvp 0qAWL1UtkND6WZVJcZq/aWsYv++So7c2Okz4K39N6/g19tCFm5+YXFRY5PNOc7/f69M7Z53x mSX9vIwrg7N6icN/r7AtSizFGYmGWsxFxYkAvXlmhv8CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for pll2650xx in samsung pll file. This pll variant is close to pll36xx but uses CON2 registers instead of CON1. Aud_pll in Exynos5260 is pll2650xx and uses this code. Signed-off-by: Rahul Sharma --- drivers/clk/samsung/clk-pll.c | 101 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 2 +- 2 files changed, 102 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 237a889..60c5679 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -811,6 +811,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = { .recalc_rate = samsung_pll2550xx_recalc_rate, }; +/* + * PLL2650XX Clock Type + */ + +/* Maximum lock time can be 3000 * PDIV cycles */ +#define PLL2650XX_LOCK_FACTOR (3000) + +#define PLL2650XX_MDIV_SHIFT (9) +#define PLL2650XX_PDIV_SHIFT (3) +#define PLL2650XX_SDIV_SHIFT (0) +#define PLL2650XX_KDIV_SHIFT (0) +#define PLL2650XX_MDIV_MASK (0x1ff) +#define PLL2650XX_PDIV_MASK (0x3f) +#define PLL2650XX_SDIV_MASK (0x7) +#define PLL2650XX_KDIV_MASK (0xffff) +#define PLL2650XX_PLL_ENABLE_SHIFT (23) +#define PLL2650XX_PLL_LOCKTIME_SHIFT (21) +#define PLL2650XX_PLL_FOUTMASK_SHIFT (31) + +static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; + s16 kdiv; + u64 fvco = parent_rate; + + pll_con0 = __raw_readl(pll->con_reg); + pll_con2 = __raw_readl(pll->con_reg + 8); + mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK; + pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK; + sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; + kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK); + + fvco *= (mdiv << 16) + kdiv; + do_div(fvco, (pdiv << sdiv)); + fvco >>= 16; + + return (unsigned long)fvco; +} + +static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp, pll_con0, pll_con2; + const struct samsung_pll_rate_table *rate; + + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + pll_con0 = __raw_readl(pll->con_reg); + pll_con2 = __raw_readl(pll->con_reg + 8); + + /* Change PLL PMS values */ + pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | + PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT | + PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT); + pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; + pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; + pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; + pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT; + pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT; + + pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT); + pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) + << PLL2650XX_KDIV_SHIFT; + + /* Set PLL lock time. */ + __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); + + __raw_writel(pll_con0, pll->con_reg); + __raw_writel(pll_con2, pll->con_reg + 8); + + do { + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT))); + + return 0; +} + +static const struct clk_ops samsung_pll2650xx_clk_ops = { + .recalc_rate = samsung_pll2650xx_recalc_rate, + .set_rate = samsung_pll2650xx_set_rate, + .round_rate = samsung_pll_round_rate, +}; + +static const struct clk_ops samsung_pll2650xx_clk_min_ops = { + .recalc_rate = samsung_pll2650xx_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, struct samsung_pll_clock *pll_clk, void __iomem *base) @@ -894,6 +989,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_pll2550xx_clk_ops; break; + case pll_2650xx: + if (!pll->rate_table) + init.ops = &samsung_pll2650xx_clk_min_ops; + else + init.ops = &samsung_pll2650xx_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index e106470..b326e94 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -26,6 +26,7 @@ enum samsung_pll_type { pll_6552, pll_6553, pll_2550xx, + pll_2650xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \ @@ -93,5 +94,4 @@ struct samsung_pll_rate_table { extern struct clk * __init samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset); - #endif /* __SAMSUNG_CLK_PLL_H */