From patchwork Tue Feb 18 11:56:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 3669281 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0808DBF40C for ; Tue, 18 Feb 2014 11:57:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2475A20213 for ; Tue, 18 Feb 2014 11:57:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 13CF3201FE for ; Tue, 18 Feb 2014 11:57:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755033AbaBRL46 (ORCPT ); Tue, 18 Feb 2014 06:56:58 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:28361 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754953AbaBRL45 (ORCPT ); Tue, 18 Feb 2014 06:56:57 -0500 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N16008NOX6W8H40@mailout4.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 18 Feb 2014 20:56:56 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 91.F3.09028.88A43035; Tue, 18 Feb 2014 20:56:56 +0900 (KST) X-AuditID: cbfee68e-b7f566d000002344-df-53034a888b94 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id D0.36.29263.88A43035; Tue, 18 Feb 2014 20:56:56 +0900 (KST) Received: from localhost.localdomain ([107.108.83.245]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N1600LX2X6HOT60@mmp1.samsung.com>; Tue, 18 Feb 2014 20:56:56 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, r.sh.open@gmail.com, Pankaj Dubey , Rahul Sharma Subject: [PATCH v3 2/5] clk/samsung: add support for pll2550xx Date: Tue, 18 Feb 2014 17:26:07 +0530 Message-id: <1392724570-27977-3-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1392724570-27977-1-git-send-email-rahul.sharma@samsung.com> References: <1392724570-27977-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHLMWRmVeSWpSXmKPExsWyRsSkSrfDiznYYN07KYvvu76wW/QuuMpm senxNVaLGef3MVk8nXCRzWLRVqDEwhfxFlMWHWa1WLXrD6MDp8fOWXfZPe5c28PmsXlJvUff llWMHp83yQWwRnHZpKTmZJalFunbJXBl3Fg3jbHgtUrF3ZUbWRsY98h1MXJySAiYSCzvbWOC sMUkLtxbz9bFyMUhJLCUUaLnzHs2mKLDC/ZCJRYxSnSefcsI4bQzSfx91MoKUsUmoCsx++Az RhBbRMBbYvKZv+wgRcwCxxklfr//BDZKWMBOYm7TSWYQm0VAVWLlxi9gu3kFPCS2LbwDFOcA WqcgMWeSDYjJKeApsetDEkiFEFDF3PMrWUBGSgisYpf4930/E8QYAYlvkw+xQLTKSmw6wAxx tKTEwRU3WCYwCi9gZFjFKJpakFxQnJReZKRXnJhbXJqXrpecn7uJERj2p/8969vBePOA9SHG ZKBxE5mlRJPzgXGTVxJvaGxmZGFqYmpsZG5pRpqwkjjvoodJQUIC6YklqdmpqQWpRfFFpTmp xYcYmTg4pRoY45i/hxas80kqPaX+OvHup462eWdF+Cuv7P+sY/tUd8LkyJgzU7Jd7tcfbHW/ a5RuzNtTklWduMFTYsHaFYfF5xz48NjhvdJKviRhQ6Pw/ZXW3ncy7OdOr+OKmKYllSoYxrLl zbrQk+Ehk3ae5d1vPEF69YI3XKZ7+/suTTT1NWZU/c48+6eeEktxRqKhFnNRcSIA3o/eUZEC AAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrNIsWRmVeSWpSXmKPExsVy+t9jAd0OL+Zggw1/BC2+7/rCbtG74Cqb xabH11gtZpzfx2TxdMJFNotFW4ESC1/EW0xZdJjVYtWuP4wOnB47Z91l97hzbQ+bx+Yl9R59 W1YxenzeJBfAGtXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+Ti E6DrlpkDdI+SQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0kLCGMePGummMBa9V Ku6u3MjawLhHrouRk0NCwETi8IK9bBC2mMSFe+uBbC4OIYFFjBKdZ98yQjjtTBJ/H7WyglSx CehKzD74jBHEFhHwlph85i87SBGzwHFGid/vP4GNEhawk5jbdJIZxGYRUJVYufELE4jNK+Ah sW3hHaA4B9A6BYk5k2xATE4BT4ldH5JAKoSAKuaeX8kygZF3ASPDKkbR1ILkguKk9FxDveLE 3OLSvHS95PzcTYzgqHomtYNxZYPFIUYBDkYlHt4PykzBQqyJZcWVuYcYJTiYlUR4/cyYg4V4 UxIrq1KL8uOLSnNSiw8xJgPdNJFZSjQ5HxjxeSXxhsYm5qbGppYmFiZmlqQJK4nzHmi1DhQS SE8sSc1OTS1ILYLZwsTBKdXA2Lr25x2OezICAWVqDsEdkg8fZl1/UnVj9pFTCbLtFw83/imf ers021f7liaT3GMJHecb1cWy3i67zZ+vb9XdZrGx8Q1D3e79qaXdVjxRb2NOGK6OWLJHofZh 3tquR/76TSyL52cefGg7/0pqietpW7efi+fP9Xk74V9sgMTsbdnxihHn1PevVmIpzkg01GIu Kk4EAPCbSl/uAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Pankaj Dubey exynos5260 use pll2550xx and it has different bit fields for P,M,S values as compared to pll2550. Support for pll2550xx is added here. Signed-off-by: Pankaj Dubey Signed-off-by: Rahul Sharma Signed-off-by: Arun Kumar K --- drivers/clk/samsung/clk-pll.c | 108 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 109 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index dced769..56b3fbe 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -710,6 +710,108 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, return clk; } +/* + * PLL2550xx Clock Type + */ + +/* Maximum lock time can be 270 * PDIV cycles */ +#define PLL2550XX_LOCK_FACTOR 270 + +#define PLL2550XX_M_MASK 0x3FF +#define PLL2550XX_P_MASK 0x3F +#define PLL2550XX_S_MASK 0x7 +#define PLL2550XX_LOCK_STAT_MASK 0x1 +#define PLL2550XX_M_SHIFT 9 +#define PLL2550XX_P_SHIFT 3 +#define PLL2550XX_S_SHIFT 0 +#define PLL2550XX_LOCK_STAT_SHIFT 21 + +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, pll_con; + u64 fvco = parent_rate; + + pll_con = __raw_readl(pll->con_reg); + mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; + pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; + sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) +{ + u32 old_mdiv, old_pdiv; + + old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; + old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; + + return mdiv != old_mdiv || pdiv != old_pdiv; +} + +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 tmp; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + tmp = __raw_readl(pll->con_reg); + + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { + /* If only s change, change just s value only*/ + tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT); + tmp |= rate->sdiv << PLL2550XX_S_SHIFT; + __raw_writel(tmp, pll->con_reg); + + return 0; + } + + /* Set PLL lock time. */ + __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); + + /* Change PLL PMS values */ + tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) | + (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) | + (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT)); + tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | + (rate->pdiv << PLL2550XX_P_SHIFT) | + (rate->sdiv << PLL2550XX_S_SHIFT); + __raw_writel(tmp, pll->con_reg); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK + << PLL2550XX_LOCK_STAT_SHIFT))); + + return 0; +} + +static const struct clk_ops samsung_pll2550xx_clk_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll2550xx_set_rate, +}; + +static const struct clk_ops samsung_pll2550xx_clk_min_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, struct samsung_pll_clock *pll_clk, void __iomem *base) @@ -787,6 +889,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_pll46xx_clk_ops; break; + case pll_2550xx: + if (!pll->rate_table) + init.ops = &samsung_pll2550xx_clk_min_ops; + else + init.ops = &samsung_pll2550xx_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 6c39030..e106470 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -25,6 +25,7 @@ enum samsung_pll_type { pll_4650c, pll_6552, pll_6553, + pll_2550xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \