From patchwork Tue Feb 18 11:56:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 3669301 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D54109F2EC for ; Tue, 18 Feb 2014 11:57:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DEE45201FE for ; Tue, 18 Feb 2014 11:57:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2432C20212 for ; Tue, 18 Feb 2014 11:57:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755039AbaBRL47 (ORCPT ); Tue, 18 Feb 2014 06:56:59 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:11520 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754311AbaBRL46 (ORCPT ); Tue, 18 Feb 2014 06:56:58 -0500 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N16007MNX6XTCD0@mailout2.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 18 Feb 2014 20:56:58 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.126]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id AE.0B.14803.98A43035; Tue, 18 Feb 2014 20:56:57 +0900 (KST) X-AuditID: cbfee691-b7efc6d0000039d3-50-53034a890950 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id A1.36.29263.98A43035; Tue, 18 Feb 2014 20:56:57 +0900 (KST) Received: from localhost.localdomain ([107.108.83.245]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N1600LX2X6HOT60@mmp1.samsung.com>; Tue, 18 Feb 2014 20:56:57 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [PATCH v3 3/5] clk/samsung: add support for pll2650xx Date: Tue, 18 Feb 2014 17:26:08 +0530 Message-id: <1392724570-27977-4-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1392724570-27977-1-git-send-email-rahul.sharma@samsung.com> References: <1392724570-27977-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsWyRsSkTrfTiznY4GeDtcX3XV/YLXoXXGWz 2PT4GqvFjPP7mCyeTrjIZrHwRbzFlEWHWS1W7frD6MDhsXPWXXaPO9f2sHlsXlLv0bdlFaPH 501yAaxRXDYpqTmZZalF+nYJXBmHvxxnLDiqUvFj9W7GBsa9cl2MHBwSAiYSl+czdTFyApli EhfurWfrYuTiEBJYyijxc+JdRoiEicT9zSuZIBKLGCUWLP7ECuG0M0nMebGFDaSKTUBXYvbB Z2AdIgLeEpPP/GUHKWIWmMUocXfJUnaQhLCAncSlC9PAbBYBVYmu672sIDavgIfErzmrmCFO UpCYM8kGxOQU8JTY9SEJpEIIqGLu+ZUsICMlBJaxS9z8thRqjIDEt8mHWCBaZSU2HWCGOFpS 4uCKGywTGIUXMDKsYhRNLUguKE5KLzLVK07MLS7NS9dLzs/dxAgM9dP/nk3cwXj/gPUhxmSg cROZpUST84GxklcSb2hsZmRhamJqbGRuaUaasJI4b/qjpCAhgfTEktTs1NSC1KL4otKc1OJD jEwcnFINjBeWbLe7vNL+7zw5u0lMf86HuPh0/nt4Rc9NK3kpl5bXgt+X7z1aI/pL2VxeOsPg 3sQXkUIv98U39EwJm5K1+uThquervunz3Y/ldTp+eLPqvK3Jr1g7Z92RSphUJir+lynYkFdJ YNecEocvnlf/T4jTkw7TKHv1vcx/y/mK2QGZm34a/Ky5KanEUpyRaKjFXFScCAC+CSasiwIA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGIsWRmVeSWpSXmKPExsVy+t9jAd1OL+Zgg/NfjSy+7/rCbtG74Cqb xabH11gtZpzfx2TxdMJFNouFL+Itpiw6zGqxatcfRgcOj52z7rJ73Lm2h81j85J6j74tqxg9 Pm+SC2CNamC0yUhNTEktUkjNS85PycxLt1XyDo53jjc1MzDUNbS0MFdSyEvMTbVVcvEJ0HXL zAE6RUmhLDGnFCgUkFhcrKRvh2lCaIibrgVMY4Sub0gQXI+RARpIWMOYcfjLccaCoyoVP1bv Zmxg3CvXxcjJISFgInF/80omCFtM4sK99WxdjFwcQgKLGCUWLP7ECuG0M0nMebGFDaSKTUBX YvbBZ4wgtoiAt8TkM3/ZQYqYBWYxStxdspQdJCEsYCdx6cI0MJtFQFWi63ovK4jNK+Ah8WvO KuYuRg6gdQoScybZgJicAp4Suz4kgVQIAVXMPb+SZQIj7wJGhlWMoqkFyQXFSem5hnrFibnF pXnpesn5uZsYwbH0TGoH48oGi0OMAhyMSjy8H5SZgoVYE8uKK3MPMUpwMCuJ8PqZMQcL8aYk VlalFuXHF5XmpBYfYkwGumkis5Rocj4wzvNK4g2NTcxNjU0tTSxMzCxJE1YS5z3Qah0oJJCe WJKanZpakFoEs4WJg1OqgdGf8f4ynTCOQ1oH93s8upS8/eDJPda3Xq4VD3P6K7TJ4vt/QXGn EzMaH9+JF+b333kowvLn1zOzQ74/+pQmmlDfmaHpZ6qRsVk+Q8BrnkGPbP4V3uT4wxlnzu9d 5ZZXyCzM2T/9Wr19T9zZomnC7zj2cfLZz7Bo6ZR5+iBoejjT/ftZBgVfApVYijMSDbWYi4oT AcU52zPpAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for pll2650xx in samsung pll file. This pll variant is close to pll36xx but uses CON2 registers instead of CON1. Aud_pll in Exynos5260 is pll2650xx and uses this code. Signed-off-by: Rahul Sharma --- drivers/clk/samsung/clk-pll.c | 101 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 102 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 56b3fbe..801b3dd 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -812,6 +812,101 @@ static const struct clk_ops samsung_pll2550xx_clk_min_ops = { .recalc_rate = samsung_pll2550xx_recalc_rate, }; +/* + * PLL2650XX Clock Type + */ + +/* Maximum lock time can be 3000 * PDIV cycles */ +#define PLL2650XX_LOCK_FACTOR 3000 + +#define PLL2650XX_MDIV_SHIFT 9 +#define PLL2650XX_PDIV_SHIFT 3 +#define PLL2650XX_SDIV_SHIFT 0 +#define PLL2650XX_KDIV_SHIFT 0 +#define PLL2650XX_MDIV_MASK 0x1ff +#define PLL2650XX_PDIV_MASK 0x3f +#define PLL2650XX_SDIV_MASK 0x7 +#define PLL2650XX_KDIV_MASK 0xffff +#define PLL2650XX_PLL_ENABLE_SHIFT 23 +#define PLL2650XX_PLL_LOCKTIME_SHIFT 21 +#define PLL2650XX_PLL_FOUTMASK_SHIFT 31 + +static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; + s16 kdiv; + u64 fvco = parent_rate; + + pll_con0 = __raw_readl(pll->con_reg); + pll_con2 = __raw_readl(pll->con_reg + 8); + mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK; + pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK; + sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; + kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK); + + fvco *= (mdiv << 16) + kdiv; + do_div(fvco, (pdiv << sdiv)); + fvco >>= 16; + + return (unsigned long)fvco; +} + +static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp, pll_con0, pll_con2; + const struct samsung_pll_rate_table *rate; + + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + pll_con0 = __raw_readl(pll->con_reg); + pll_con2 = __raw_readl(pll->con_reg + 8); + + /* Change PLL PMS values */ + pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | + PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT | + PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT); + pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; + pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; + pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; + pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT; + pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT; + + pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT); + pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) + << PLL2650XX_KDIV_SHIFT; + + /* Set PLL lock time. */ + __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); + + __raw_writel(pll_con0, pll->con_reg); + __raw_writel(pll_con2, pll->con_reg + 8); + + do { + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT))); + + return 0; +} + +static const struct clk_ops samsung_pll2650xx_clk_ops = { + .recalc_rate = samsung_pll2650xx_recalc_rate, + .set_rate = samsung_pll2650xx_set_rate, + .round_rate = samsung_pll_round_rate, +}; + +static const struct clk_ops samsung_pll2650xx_clk_min_ops = { + .recalc_rate = samsung_pll2650xx_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, struct samsung_pll_clock *pll_clk, void __iomem *base) @@ -895,6 +990,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_pll2550xx_clk_ops; break; + case pll_2650xx: + if (!pll->rate_table) + init.ops = &samsung_pll2650xx_clk_min_ops; + else + init.ops = &samsung_pll2650xx_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index e106470..fa9bdaf 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -26,6 +26,7 @@ enum samsung_pll_type { pll_6552, pll_6553, pll_2550xx, + pll_2650xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \