From patchwork Tue Feb 18 11:56:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 3669321 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3C3D0BF13A for ; Tue, 18 Feb 2014 11:57:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0068D201CD for ; Tue, 18 Feb 2014 11:57:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 37B8420211 for ; Tue, 18 Feb 2014 11:57:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755049AbaBRL5F (ORCPT ); Tue, 18 Feb 2014 06:57:05 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:35229 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755040AbaBRL5D (ORCPT ); Tue, 18 Feb 2014 06:57:03 -0500 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N1600J7SX719V90@mailout1.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 18 Feb 2014 20:57:02 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.125]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id C7.F3.09028.D8A43035; Tue, 18 Feb 2014 20:57:01 +0900 (KST) X-AuditID: cbfee68e-b7f566d000002344-0e-53034a8d5d2c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id F9.64.28157.C8A43035; Tue, 18 Feb 2014 20:57:00 +0900 (KST) Received: from localhost.localdomain ([107.108.83.245]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N1600LX2X6HOT60@mmp1.samsung.com>; Tue, 18 Feb 2014 20:57:00 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [PATCH v3 5/5] clk/exynos5260: add clock file for exynos5260 Date: Tue, 18 Feb 2014 17:26:10 +0530 Message-id: <1392724570-27977-6-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1392724570-27977-1-git-send-email-rahul.sharma@samsung.com> References: <1392724570-27977-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJLMWRmVeSWpSXmKPExsWyRsSkVrfXiznY4MIlEYvvu76wW/QuuMpm senxNVaLGef3MVk8nXCRzWLhi3iLKYsOs1qs2vWH0YHDY+esu+wed67tYfPYvKTeo2/LKkaP z5vkAlijuGxSUnMyy1KL9O0SuDI27v3AXPD8B2vF13/XWRoYX01i7WLk5JAQMJGY2LiHEcIW k7hwbz1bFyMXh5DAUkaJ15s/ACU4wIp2XTaBiC9ilDjzpoUVwmlnkli25xo7SDebgK7E7IPP wCaJCHhLTD7zlx2kiFlgFqPE3SVLwYqEBVwlzl47AbaaRUBVYvL1BrANvAIeEisWCEAsU5CY M8kGxOQU8JTY9SEJpFgIqGDu+ZUsIBMlBJaxS/Sf2wY1RUDi2+RDLBCtshKbDjBD/CIpcXDF DZYJjMILGBlWMYqmFiQXFCelFxnpFSfmFpfmpesl5+duYgQG++l/z/p2MN48YH2IMRlo3ERm KdHkfGC05JXEGxqbGVmYmpgaG5lbmpEmrCTOu+hhUpCQQHpiSWp2ampBalF8UWlOavEhRiYO TqkGxuX9qj9K7E/Jukik3Izrlpp6O29hNHM/t+ul/M4LUe+2d7crKaz2lH/J42m3dVHD99eJ i9ytr29Ze/b2s30fy3w1Pie4fNh0u+9L5Fszd0Fvienv677eihH5vkjFk8O9dVtyw4LlntVT ffdYBLglrPzW9LnS8OrvL5Pm6x8oltMpXL9OTrP6ixJLcUaioRZzUXEiACGyapiMAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGIsWRmVeSWpSXmKPExsVy+t9jAd0eL+Zgg0PNVhbfd31ht+hdcJXN YtPja6wWM87vY7J4OuEim8XCF/EWUxYdZrVYtesPowOHx85Zd9k97lzbw+axeUm9R9+WVYwe nzfJBbBGNTDaZKQmpqQWKaTmJeenZOal2yp5B8c7x5uaGRjqGlpamCsp5CXmptoqufgE6Lpl 5gCdoqRQlphTChQKSCwuVtK3wzQhNMRN1wKmMULXNyQIrsfIAA0krGHM2Lj3A3PB8x+sFV// XWdpYHw1ibWLkYNDQsBEYtdlky5GTiBTTOLCvfVsXYxcHEICixglzrxpYYVw2pkklu25xg5S xSagKzH74DNGEFtEwFti8pm/7CBFzAKzGCXuLlkKViQs4Cpx9toJVhCbRUBVYvL1BkaQbbwC HhIrFghALFaQmDPJBsTkFPCU2PUhCaRYCKhg7vmVLBMYeRcwMqxiFE0tSC4oTkrPNdIrTswt Ls1L10vOz93ECI6lZ9I7GFc1WBxiFOBgVOLh/aDMFCzEmlhWXJl7iFGCg1lJhNfPjDlYiDcl sbIqtSg/vqg0J7X4EGMy0EkTmaVEk/OBcZ5XEm9obGJuamxqaWJhYmZJmrCSOO/BVutAIYH0 xJLU7NTUgtQimC1MHJxSQE97KN5VWq/4gTXh1Y31K8rNGoKWPHPfluY7b+oRx57jFvGGcTN9 G/z3c3p3Pgo6dP3uU2vRt0VfK5J3HpCrWvvzjHrb9vtfrK2nJXu4v1wYH1AmIK6iNktnbXfg 84ZWn9au7Ss65ARDlsc+ExB+W/A14YG9jsf0B3vZJj6zip2mK9+06h+biRJLcUaioRZzUXEi AMBpy0zpAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for exynos5260 clocks in clock driver. Signed-off-by: Rahul Sharma Signed-off-by: Pankaj Dubey --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5260.c | 2235 ++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-exynos5260.h | 480 ++++++++ 3 files changed, 2716 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos5260.c create mode 100644 drivers/clk/samsung/clk-exynos5260.h diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 8eb4799..f791b31 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o +obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c new file mode 100644 index 0000000..bcb633e --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5260.c @@ -0,0 +1,2235 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Exynos5260 SoC. +*/ + +#include +#include +#include +#include +#include +#include + +#include "clk-exynos5260.h" +#include "clk.h" +#include "clk-pll.h" + +#include + +static LIST_HEAD(clock_reg_cache_list); +static bool syscore_ops_registered; + +struct exynos5260_clock_reg_cache { + struct list_head node; + void __iomem *reg_base; + struct samsung_clk_reg_dump *rdump; + unsigned int rd_num; +}; + +#ifdef CONFIG_PM_SLEEP + +/* + * list of controller registers to be saved and restored during a + * suspend/resume cycle. +*/ + +static unsigned long exynos5260_aud_clk_regs[] __initdata = { +/* + *Registers for CMU_AUD +*/ + MUX_SEL_AUD, + DIV_AUD0, + DIV_AUD1, + EN_ACLK_AUD, + EN_PCLK_AUD, + EN_SCLK_AUD, + EN_IP_AUD, +}; + +static unsigned long exynos5260_disp_clk_regs[] __initdata = { +/* + *Registers for CMU_DISP +*/ + MUX_SEL_DISP0, + MUX_SEL_DISP1, + MUX_SEL_DISP2, + MUX_SEL_DISP3, + MUX_SEL_DISP4, + DIV_DISP, + EN_ACLK_DISP, + EN_PCLK_DISP, + EN_SCLK_DISP0, + EN_SCLK_DISP1, + EN_IP_DISP, + EN_IP_DISP_BUS, +}; + +static unsigned long exynos5260_egl_clk_regs[] __initdata = { +/* + *Registers for CMU_EGL +*/ + EGL_PLL_LOCK, + EGL_PLL_CON0, + EGL_PLL_CON1, + EGL_PLL_FREQ_DET, + MUX_SEL_EGL, + MUX_ENABLE_EGL, + DIV_EGL, + DIV_EGL_PLL_FDET, + EN_ACLK_EGL, + EN_PCLK_EGL, + EN_SCLK_EGL, +}; + +static unsigned long exynos5260_fsys_clk_regs[] __initdata = { +/* + *Registers for CMU_FSYS +*/ + MUX_SEL_FSYS0, + MUX_SEL_FSYS1, + EN_ACLK_FSYS, + EN_ACLK_FSYS_SECURE_RTIC, + EN_ACLK_FSYS_SECURE_SMMU_RTIC, + EN_SCLK_FSYS, + EN_IP_FSYS, + EN_IP_FSYS_SECURE_RTIC, + EN_IP_FSYS_SECURE_SMMU_RTIC, +}; + +static unsigned long exynos5260_g2d_clk_regs[] __initdata = { +/* + *Registers for CMU_G2D +*/ + MUX_SEL_G2D, + MUX_STAT_G2D, + DIV_G2D, + EN_ACLK_G2D, + EN_ACLK_G2D_SECURE_SSS, + EN_ACLK_G2D_SECURE_SLIM_SSS, + EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS, + EN_ACLK_G2D_SECURE_SMMU_SSS, + EN_ACLK_G2D_SECURE_SMMU_MDMA, + EN_ACLK_G2D_SECURE_SMMU_G2D, + EN_PCLK_G2D, + EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS, + EN_PCLK_G2D_SECURE_SMMU_SSS, + EN_PCLK_G2D_SECURE_SMMU_MDMA, + EN_PCLK_G2D_SECURE_SMMU_G2D, + EN_IP_G2D, + EN_IP_G2D_SECURE_SSS, + EN_IP_G2D_SECURE_SLIM_SSS, + EN_IP_G2D_SECURE_SMMU_SLIM_SSS, + EN_IP_G2D_SECURE_SMMU_SSS, + EN_IP_G2D_SECURE_SMMU_MDMA, + EN_IP_G2D_SECURE_SMMU_G2D, +}; + +static unsigned long exynos5260_g3d_clk_regs[] __initdata = { +/* + *Registers for CMU_G3D +*/ + G3D_PLL_LOCK, + G3D_PLL_CON0, + G3D_PLL_CON1, + G3D_PLL_FDET, + MUX_SEL_G3D, + DIV_G3D, + DIV_G3D_PLL_FDET, + EN_ACLK_G3D, + EN_PCLK_G3D, + EN_SCLK_G3D, + EN_IP_G3D, +}; + +static unsigned long exynos5260_gscl_clk_regs[] __initdata = { +/* + *Registers for CMU_GSCL +*/ + MUX_SEL_GSCL, + DIV_GSCL, + EN_ACLK_GSCL, + EN_ACLK_GSCL_FIMC, + EN_ACLK_GSCL_SECURE_SMMU_GSCL0, + EN_ACLK_GSCL_SECURE_SMMU_GSCL1, + EN_ACLK_GSCL_SECURE_SMMU_MSCL0, + EN_ACLK_GSCL_SECURE_SMMU_MSCL1, + EN_PCLK_GSCL, + EN_PCLK_GSCL_FIMC, + EN_PCLK_GSCL_SECURE_SMMU_GSCL0, + EN_PCLK_GSCL_SECURE_SMMU_GSCL1, + EN_PCLK_GSCL_SECURE_SMMU_MSCL0, + EN_PCLK_GSCL_SECURE_SMMU_MSCL1, + EN_SCLK_GSCL, + EN_SCLK_GSCL_FIMC, + EN_IP_GSCL, + EN_IP_GSCL_FIMC, + EN_IP_GSCL_SECURE_SMMU_GSCL0, + EN_IP_GSCL_SECURE_SMMU_GSCL1, + EN_IP_GSCL_SECURE_SMMU_MSCL0, + EN_IP_GSCL_SECURE_SMMU_MSCL1, +}; + +static unsigned long exynos5260_isp_clk_regs[] __initdata = { +/* + *Registers for CMU_ISP +*/ + MUX_SEL_ISP0, + MUX_SEL_ISP1, + DIV_ISP, + EN_ACLK_ISP0, + EN_ACLK_ISP1, + EN_PCLK_ISP0, + EN_PCLK_ISP1, + EN_SCLK_ISP, + EN_IP_ISP0, + EN_IP_ISP1, +}; + +static unsigned long exynos5260_kfc_clk_regs[] __initdata = { +/* + *Registers for CMU_KFC +*/ + KFC_PLL_LOCK, + KFC_PLL_CON0, + KFC_PLL_CON1, + KFC_PLL_FDET, + MUX_SEL_KFC0, + MUX_SEL_KFC2, + DIV_KFC, + DIV_KFC_PLL_FDET, + EN_ACLK_KFC, + EN_PCLK_KFC, + EN_SCLK_KFC, + EN_IP_KFC, +}; + +static unsigned long exynos5260_mfc_clk_regs[] __initdata = { +/* + *Registers for CMU_MFC +*/ + MUX_SEL_MFC, + DIV_MFC, + EN_ACLK_MFC, + EN_ACLK_SECURE_SMMU2_MFC, + EN_PCLK_MFC, + EN_PCLK_SECURE_SMMU2_MFC, + EN_IP_MFC, + EN_IP_MFC_SECURE_SMMU2_MFC, +}; + +static unsigned long exynos5260_mif_clk_regs[] __initdata = { +/* + *Registers for CMU_MIF +*/ + MEM_PLL_LOCK, + BUS_PLL_LOCK, + MEDIA_PLL_LOCK, + MEM_PLL_CON0, + MEM_PLL_CON1, + MEM_PLL_FDET, + BUS_PLL_CON0, + BUS_PLL_CON1, + BUS_PLL_FDET, + MEDIA_PLL_CON0, + MEDIA_PLL_CON1, + MEDIA_PLL_FDET, + MUX_SEL_MIF, + DIV_MIF, + DIV_MIF_PLL_FDET, + EN_ACLK_MIF, + EN_ACLK_MIF_SECURE_DREX1_TZ, + EN_ACLK_MIF_SECURE_DREX0_TZ, + EN_ACLK_MIF_SECURE_INTMEM, + EN_PCLK_MIF, + EN_PCLK_MIF_SECURE_MONOCNT, + EN_PCLK_MIF_SECURE_RTC_APBIF, + EN_PCLK_MIF_SECURE_DREX1_TZ, + EN_PCLK_MIF_SECURE_DREX0_TZ, + EN_SCLK_MIF, + EN_IP_MIF, + EN_IP_MIF_SECURE_MONOCNT, + EN_IP_MIF_SECURE_RTC_APBIF, + EN_IP_MIF_SECURE_DREX1_TZ, + EN_IP_MIF_SECURE_DREX0_TZ, + EN_IP_MIF_SECURE_INTEMEM, +}; + +static unsigned long exynos5260_peri_clk_regs[] __initdata = { +/* + *Registers for CMU_PERI +*/ + MUX_SEL_PERI, + MUX_SEL_PERI1, + DIV_PERI, + EN_PCLK_PERI0, + EN_PCLK_PERI1, + EN_PCLK_PERI2, + EN_PCLK_PERI3, + EN_PCLK_PERI_SECURE_CHIPID, + EN_PCLK_PERI_SECURE_PROVKEY0, + EN_PCLK_PERI_SECURE_PROVKEY1, + EN_PCLK_PERI_SECURE_SECKEY, + EN_PCLK_PERI_SECURE_ANTIRBKCNT, + EN_PCLK_PERI_SECURE_TOP_RTC, + EN_PCLK_PERI_SECURE_TZPC, + EN_SCLK_PERI, + EN_SCLK_PERI_SECURE_TOP_RTC, + EN_IP_PERI0, + EN_IP_PERI1, + EN_IP_PERI2, + EN_IP_PERI_SECURE_CHIPID, + EN_IP_PERI_SECURE_PROVKEY0, + EN_IP_PERI_SECURE_PROVKEY1, + EN_IP_PERI_SECURE_SECKEY, + EN_IP_PERI_SECURE_ANTIRBKCNT, + EN_IP_PERI_SECURE_TOP_RTC, + EN_IP_PERI_SECURE_TZPC, +}; + +static unsigned long exynos5260_top_clk_regs[] __initdata = { +/* + *Registers for CMU_TOP +*/ + DISP_PLL_LOCK, + AUD_PLL_LOCK, + DISP_PLL_CON0, + DISP_PLL_CON1, + DISP_PLL_FDET, + AUD_PLL_CON0, + AUD_PLL_CON1, + AUD_PLL_CON2, + AUD_PLL_FDET, + MUX_SEL_TOP_PLL0, + MUX_SEL_TOP_MFC, + MUX_SEL_TOP_G2D, + MUX_SEL_TOP_GSCL, + MUX_SEL_TOP_ISP10, + MUX_SEL_TOP_ISP11, + MUX_SEL_TOP_DISP0, + MUX_SEL_TOP_DISP1, + MUX_SEL_TOP_BUS, + MUX_SEL_TOP_PERI0, + MUX_SEL_TOP_PERI1, + MUX_SEL_TOP_FSYS, + DIV_TOP_G2D_MFC, + DIV_TOP_GSCL_ISP0, + DIV_TOP_ISP10, + DIV_TOP_ISP11, + DIV_TOP_DISP, + DIV_TOP_BUS, + DIV_TOP_PERI0, + DIV_TOP_PERI1, + DIV_TOP_PERI2, + DIV_TOP_FSYS0, + DIV_TOP_FSYS1, + DIV_TOP_HPM, + DIV_TOP_PLL_FDET, + EN_ACLK_TOP, + EN_SCLK_TOP, + EN_IP_TOP, +}; + +static int exynos5260_clk_suspend(void) +{ + struct exynos5260_clock_reg_cache *cache; + + list_for_each_entry(cache, &clock_reg_cache_list, node) + samsung_clk_save(cache->reg_base, cache->rdump, + cache->rd_num); + + return 0; +} + +static void exynos5260_clk_resume(void) +{ + struct exynos5260_clock_reg_cache *cache; + + list_for_each_entry(cache, &clock_reg_cache_list, node) + samsung_clk_restore(cache->reg_base, cache->rdump, + cache->rd_num); +} + +static struct syscore_ops exynos5260_clk_syscore_ops = { + .suspend = exynos5260_clk_suspend, + .resume = exynos5260_clk_resume, +}; + +static void exynos5260_clk_sleep_init(void __iomem *reg_base, + unsigned long *rdump, + unsigned long nr_rdump) +{ + struct exynos5260_clock_reg_cache *reg_cache; + + reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache), + GFP_KERNEL); + if (!reg_cache) + panic("could not allocate register cache.\n"); + + reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump); + + if (!reg_cache->rdump) + panic("could not allocate register dump storage.\n"); + + reg_cache->rd_num = nr_rdump; + reg_cache->reg_base = reg_base; + list_add_tail(®_cache->node, &clock_reg_cache_list); + + if (!syscore_ops_registered) { + register_syscore_ops(&exynos5260_clk_syscore_ops); + syscore_ops_registered = true; + } + + exynos5260_clk_suspend(); +} + +#else +static void exynos5260_clk_sleep_init(void) {} +#endif + +/* + * List of parent clocks for muses in CMU_AUD +*/ +PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"}; +PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_audcdclk0_user"}; +PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_audcdclk0_user"}; + +/* + * List of parent clocks for muses in CMU_DISP +*/ +PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll", + "phyclk_dptx_phy_ch3_txd_clk"}; +PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll", + "phyclk_dptx_phy_ch2_txd_clk"}; +PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll", + "phyclk_dptx_phy_ch1_txd_clk"}; +PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll", + "phyclk_dptx_phy_ch0_txd_clk"}; + +PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"}; +PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"}; +PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"}; +PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll", + "phyclk_hdmi_phy_tmds_clko"}; +PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll", + "phyclk_hdmi_phy_ref_clko"}; +PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll", + "phyclk_hdmi_phy_pixel_clko"}; +PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll", + "phyclk_hdmi_link_o_tmds_clkhi"}; +PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll", + "phyclk_mipi_dphy_4l_m_txbyte_clkhs"}; +PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll", + "phyclk_dptx_phy_o_ref_clk_24m"}; +PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll", + "phyclk_dptx_phy_clk_div2"}; +PNAME(mout_sclk_dsim1_tx_clk_esc_clk_user_p) = {"fin_pll", + "sclk_dsim1_txclkescclk"}; +PNAME(mout_sclk_dsim1_tx_clk_esc3_user_p) = {"fin_pll", + "sclk_dsim1_txclkesc3"}; +PNAME(mout_sclk_dsim1_tx_clk_esc2_user_p) = {"fin_pll", + "sclk_dsim1_txclkesc2"}; +PNAME(mout_sclk_dsim1_tx_clk_esc1_user_p) = {"fin_pll", + "sclk_dsim1_txclkesc1"}; +PNAME(mout_sclk_dsim1_tx_clk_esc0_user_p) = {"fin_pll", + "sclk_dsim1_txclkesc0"}; +PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user", + "mout_aclk_disp_222_user"}; +PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll", + "phyclk_mipi_dphy_4l_m_rxclkesc0"}; +PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk", + "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; + +/* + * List of parent clocks for muses in CMU_EGL +*/ +PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"}; +PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"}; + +/* + * List of parent clocks for muses in CMU_FSYS +*/ +PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll", + "phyclk_usbhost20_phy_phyclock"}; +PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll", + "phyclk_usbhost20_phy_freeclk"}; +PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll", + "phyclk_usbhost20_phy_clk48mohci"}; +PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll", + "phyclk_usbdrd30_udrd30_pipe_pclk"}; +PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll", + "phyclk_usbdrd30_udrd30_phyclock"}; + +/* + * List of parent clocks for muses in CMU_G2D +*/ +PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"}; + +/* + * List of parent clocks for muses in CMU_G3D +*/ +PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"}; + +/* + * List of parent clocks for muses in CMU_GSCL +*/ +PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "fout_aud_pll"}; +PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; +PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; +PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"}; + +/* + * List of parent clocks for muses in CMU_ISP +*/ +PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"}; +PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"}; + +/* + * List of parent clocks for muses in CMU_KFC +*/ +PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"}; +PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"}; + +/* + * List of parent clocks for muses in CMU_MFC +*/ +PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"}; + +/* + * List of parent clocks for muses in CMU_MIF +*/ +PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"}; +PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"}; +PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"}; +PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"}; +PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"}; +PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"}; +PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"}; + +/* + * List of parent clocks for muses in CMU_PERI +*/ +PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud", + "phyclk_hdmi_phy_ref_cko"}; +PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud", + "phyclk_hdmi_phy_ref_cko"}; +PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extlk", "fin_pll", + "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; + +/* + * List of parent clocks for muses in CMU_TOP +*/ +PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"}; +PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"}; +PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"}; +PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"}; +PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"}; +PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"}; + +PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"}; + +PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"}; + +PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user", + "mout_gscl_bustop_333"}; +PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user", + "mout_m2m_mediatop_400"}; +PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user", + "mout_gscl_bustop_fimc"}; + +PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user", + "mout_memtop_pll_user"}; +PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"}; +PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"}; +PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"}; + +PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"}; + +PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"}; +PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"}; +PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"}; +PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"}; +PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user", + "mout_bustop_pll_user"}; +PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"}; + +PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"}; +PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"}; + +PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"}; + +PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"}; +PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a", + "mout_mediatop_pll_user"}; +PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a", + "mout_mediatop_pll_user"}; +PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a", + "mout_mediatop_pll_user"}; + +/* fixed rate clocks generated outside the soc */ +struct samsung_fixed_rate_clock exynos5260_fixed_rate_ext_clks[] __initdata = { + FRATE(FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 24000000), + FRATE(ID_NONE, "xrtcxti", NULL, CLK_IS_ROOT, 32768), + + FRATE(ID_NONE, "ioclk_audcdclk0_user", NULL, CLK_IS_ROOT, 0), + + FRATE(ID_NONE, "ioclk_pcm_extclk", NULL, CLK_IS_ROOT, 2048000), + FRATE(ID_NONE, "ioclk_aud_i2s_bclk", NULL, CLK_IS_ROOT, 2048000), + FRATE(ID_NONE, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 49152000), + FRATE(ID_NONE, "ioclk_i2s_cdclk", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "ioclk_spdif_extlk", NULL, CLK_IS_ROOT, 0), + + FRATE(ID_NONE, "ioclk_i2s_sclk", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "ioclk_spi0_clkin", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "ioclk_spi1_clkin", NULL, CLK_IS_ROOT, 0), + FRATE(ID_NONE, "ioclk_spi2_clkin", NULL, CLK_IS_ROOT, 0), + + FRATE(ID_NONE, "ioclk_mmc0_sdrdqs_in", NULL, CLK_IS_ROOT, 200000000), + + FRATE(ID_NONE, "ioclk_spi0_isp_spi_clk_in", NULL, + CLK_IS_ROOT, 50000000), + FRATE(ID_NONE, "ioclk_spi1_isp_spi_clk_in", NULL, + CLK_IS_ROOT, 50000000), + FRATE(ID_NONE, "ioclk_spi0_isp_spi_clk_out", NULL, + CLK_IS_ROOT, 50000000), + FRATE(ID_NONE, "ioclk_spi1_isp_spi_clk_out", NULL, + CLK_IS_ROOT, 50000000), +}; + +/* fixed rate clocks generated inside the soc */ +struct samsung_fixed_rate_clock exynos5260_fixed_rate_clks[] __initdata = { + FRATE(ID_NONE, "phyclk_dptx_phy_ch3_txd_clk", NULL, + CLK_IS_ROOT, 270000000), + FRATE(ID_NONE, "phyclk_dptx_phy_ch2_txd_clk", NULL, + CLK_IS_ROOT, 270000000), + FRATE(ID_NONE, "phyclk_dptx_phy_ch1_txd_clk", NULL, + CLK_IS_ROOT, 270000000), + FRATE(ID_NONE, "phyclk_dptx_phy_ch0_txd_clk", NULL, + CLK_IS_ROOT, 270000000), + FRATE(ID_NONE, "phyclk_hdmi_phy_tmds_clko", NULL, + CLK_IS_ROOT, 250000000), + FRATE(TOP_SCLK_HDMIPHY, "phyclk_hdmi_phy_pixel_clko", NULL, + CLK_IS_ROOT, 1660000000), + FRATE(ID_NONE, "phyclk_hdmi_link_o_tmds_clkhi", NULL, + CLK_IS_ROOT, 125000000), + FRATE(ID_NONE, "phyclk_mipi_dphy_4l_m_txbyteclkhs", NULL, + CLK_IS_ROOT, 187500000), + FRATE(ID_NONE, "phyclk_dptx_phy_o_ref_clk_24m", NULL, + CLK_IS_ROOT, 24000000), + FRATE(ID_NONE, "phyclk_dptx_phy_clk_div2", NULL, + CLK_IS_ROOT, 135000000), + FRATE(ID_NONE, "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, + CLK_IS_ROOT, 20000000), + FRATE(ID_NONE, "phyclk_usbhost20_phy_phyclock", NULL, + CLK_IS_ROOT, 60000000), + FRATE(ID_NONE, "phyclk_usbhost20_phy_freeclk", NULL, + CLK_IS_ROOT, 60000000), + FRATE(ID_NONE, "phyclk_usbhost20_phy_clk48mohci", NULL, + CLK_IS_ROOT, 48000000), + FRATE(ID_NONE, "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, + CLK_IS_ROOT, 125000000), + FRATE(ID_NONE, "phyclk_usbdrd30_udrd30_phyclock", NULL, + CLK_IS_ROOT, 60000000), +}; + +struct samsung_fixed_factor_clock exynos5260_fixed_factor_clks[] __initdata = { +}; + +/* MULITPLEXER CLOCKS */ + +/* + * List of Mux clocks for CMU_AUD +*/ +struct samsung_mux_clock exynos5260_aud_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, + MUX_SEL_AUD, 8, 1), + MUX(ID_NONE, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p, + MUX_SEL_AUD, 4, 1), + MUX(ID_NONE, "mout_aud_pll_user", mout_aud_pll_user_p, + MUX_SEL_AUD, 0, 1), +}; + +/* + * List of Mux clocks for CMU_DISP +*/ +struct samsung_mux_clock exynos5260_disp_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_sclk_hdmi_spdif", mout_sclk_hdmi_spdif_p, + MUX_SEL_DISP4, 4, 2), + + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc_clk_user", + mout_sclk_dsim1_tx_clk_esc_clk_user_p, + MUX_SEL_DISP2, 28, 1), + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc3_user", + mout_sclk_dsim1_tx_clk_esc3_user_p, + MUX_SEL_DISP2, 24, 1), + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc2_user", + mout_sclk_dsim1_tx_clk_esc2_user_p, + MUX_SEL_DISP2, 20, 1), + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc1_user", + mout_sclk_dsim1_tx_clk_esc1_user_p, + MUX_SEL_DISP2, 16, 1), + MUX(ID_NONE, "mout_sclk_dsim1_tx_clk_esc0_user", + mout_sclk_dsim1_tx_clk_esc0_user_p, + MUX_SEL_DISP2, 12, 1), + MUX(ID_NONE, "mout_sclk_hdmi_pixel", mout_sclk_hdmi_pixel_p, + MUX_SEL_DISP2, 4, 1), + MUX(ID_NONE, "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user", + mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p, + MUX_SEL_DISP2, 0, 1), + + MUX(ID_NONE, "mout_phyclk_hdmi_phy_tmds_clko_user", + mout_phyclk_hdmi_phy_tmds_clko_user_p, + MUX_SEL_DISP1, 28, 1), + MUX(ID_NONE, "mout_phyclk_hdmi_phy_ref_clko_user", + mout_phyclk_hdmi_phy_ref_clko_user_p, + MUX_SEL_DISP1, 24, 1), + MUX(DISP_MOUT_HDMI_PHY_PIXEL, "mout_phyclk_hdmi_phy_pixel_clko_user", + mout_phyclk_hdmi_phy_pixel_clko_user_p, + MUX_SEL_DISP1, 20, 1), + MUX(ID_NONE, "mout_phyclk_hdmi_link_o_tmds_clkhi_user", + mout_phyclk_hdmi_link_o_tmds_clkhi_user_p, + MUX_SEL_DISP1, 16, 1), + MUX(ID_NONE, "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs", + mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, + MUX_SEL_DISP1, 8, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_o_ref_clk_24m_user", + mout_phyclk_dptx_phy_o_ref_clk_24m_user_p, + MUX_SEL_DISP1, 4, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_clk_div2_user", + mout_phyclk_dptx_phy_clk_div2_user_p, + MUX_SEL_DISP1, 0, 1), + + MUX(ID_NONE, "mout_phyclk_dptx_phy_ch3_txd_clk_user", + mout_phyclk_dptx_phy_ch3_txd_clk_user_p, + MUX_SEL_DISP0, 28, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_ch2_txd_clk_user", + mout_phyclk_dptx_phy_ch2_txd_clk_user_p, + MUX_SEL_DISP0, 24, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_ch1_txd_clk_user", + mout_phyclk_dptx_phy_ch1_txd_clk_user_p, + MUX_SEL_DISP0, 20, 1), + MUX(ID_NONE, "mout_phyclk_dptx_phy_ch0_txd_clk_user", + mout_phyclk_dptx_phy_ch0_txd_clk_user_p, + MUX_SEL_DISP0, 16, 1), + MUX(ID_NONE, "mout_aclk_disp_222_user", mout_aclk_disp_222_user_p, + MUX_SEL_DISP0, 8, 1), + MUX(ID_NONE, "mout_sclk_disp_pixel_user", mout_sclk_disp_pixel_user_p, + MUX_SEL_DISP0, 4, 1), + MUX(ID_NONE, "mout_aclk_disp_333_user", mout_aclk_disp_333_user_p, + MUX_SEL_DISP0, 0, 1), +}; + +/* + * List of Mux clocks for CMU_EGL +*/ +struct samsung_mux_clock exynos5260_egl_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1), + MUX(ID_NONE, "mout_egl_pll", mout_egl_pll_p, MUX_SEL_EGL, 4, 1), +}; + +/* + * List of Mux clocks for CMU_FSYS +*/ +struct samsung_mux_clock exynos5260_fsys_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_phyclk_usbhost20_phyclk_user", + mout_phyclk_usbhost20_phyclk_user_p, + MUX_SEL_FSYS1, 16, 1), + MUX(ID_NONE, "mout_phyclk_usbhost20_freeclk_user", + mout_phyclk_usbhost20_freeclk_user_p, + MUX_SEL_FSYS1, 12, 1), + MUX(ID_NONE, "mout_phyclk_usbhost20_clk48mohci_user", + mout_phyclk_usbhost20_clk48mohci_user_p, + MUX_SEL_FSYS1, 8, 1), + MUX(ID_NONE, "mout_phyclk_usbdrd30_pipe_pclk_user", + mout_phyclk_usbdrd30_pipe_pclk_user_p, + MUX_SEL_FSYS1, 4, 1), + MUX(ID_NONE, "mout_phyclk_usbdrd30_phyclock_user", + mout_phyclk_usbdrd30_phyclock_user_p, + MUX_SEL_FSYS1, 0, 1), +}; + +/* + * List of Mux clocks for CMU_G2D +*/ +struct samsung_mux_clock exynos5260_g2d_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_aclk_g2d_333_user", mout_aclk_g2d_333_user_p, + MUX_SEL_G2D, 0, 1), +}; + +/* + * List of Mux clocks for CMU_G3D +*/ +struct samsung_mux_clock exynos5260_g3d_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_g3d_pll", mout_g3d_pll_p, MUX_SEL_G3D, 0, 1), +}; + +/* + * List of Mux clocks for CMU_GSCL +*/ +struct samsung_mux_clock exynos5260_gscl_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_aclk_csis", mout_aclk_csis_p, MUX_SEL_GSCL, 24, 1), + MUX(ID_NONE, "mout_aclk_gscl_fimc_user", mout_aclk_gscl_fimc_user_p, + MUX_SEL_GSCL, 8, 1), + MUX(ID_NONE, "mout_aclk_m2m_400_user", mout_aclk_m2m_400_user_p, + MUX_SEL_GSCL, 4, 1), + MUX(ID_NONE, "mout_aclk_gscl_333_user", mout_aclk_gscl_333_user_p, + MUX_SEL_GSCL, 0, 1), +}; + +/* + * List of Mux clocks for CMU_ISP +*/ +struct samsung_mux_clock exynos5260_isp_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_isp_400_user", mout_isp_400_user_p, + MUX_SEL_ISP0, 4, 1), + MUX(ID_NONE, "mout_isp_266_user", mout_isp_266_user_p, + MUX_SEL_ISP0, 0, 1), +}; + +/* + * List of Mux clocks for CMU_KFC +*/ +struct samsung_mux_clock exynos5260_kfc_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_kfc_pll", mout_kfc_pll_p, MUX_SEL_KFC0, 0, 1), + MUX(ID_NONE, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1), +}; + +/* + * List of Mux clocks for CMU_MFC +*/ +struct samsung_mux_clock exynos5260_mfc_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_aclk_mfc_333_user", mout_aclk_mfc_333_user_p, + MUX_SEL_MFC, 0, 1), +}; + +/* + * List of Mux clocks for CMU_MIF +*/ +struct samsung_mux_clock exynos5260_mif_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_clk2x_phy", mout_clk2x_phy_p, MUX_SEL_MIF, 24, 1), + MUX(ID_NONE, "mout_mif_drex2x", mout_mif_drex2x_p, MUX_SEL_MIF, 20, 1), + MUX(ID_NONE, "mout_clkm_phy", mout_clkm_phy_p, MUX_SEL_MIF, 16, 1), + MUX(ID_NONE, "mout_mif_drex", mout_mif_drex_p, MUX_SEL_MIF, 12, 1), + MUX(ID_NONE, "mout_media_pll", mout_media_pll_p, MUX_SEL_MIF, 8, 1), + MUX(ID_NONE, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF, 4, 1), + MUX(ID_NONE, "mout_mem_pll", mout_mem_pll_p, MUX_SEL_MIF, 0, 1), +}; + +/* + * List of Mux clocks for CMU_PERI +*/ +struct samsung_mux_clock exynos5260_peri_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_sclk_spdif", mout_sclk_spdif_p, + MUX_SEL_PERI1, 20, 2), + MUX(ID_NONE, "mout_sclk_i2scod", mout_sclk_i2scod_p, + MUX_SEL_PERI1, 12, 2), + MUX(ID_NONE, "mout_sclk_pcm", mout_sclk_pcm_p, + MUX_SEL_PERI1, 4, 2), +}; + +/* + * List of Mux clocks for CMU_TOP +*/ +struct samsung_mux_clock exynos5260_top_mux_clks[] __initdata = { + MUX(ID_NONE, "mout_audtop_pll_user", mout_audtop_pll_user_p, + MUX_SEL_TOP_PLL0, 24, 1), + MUX(ID_NONE, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP_PLL0, 16, 1), + MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, + MUX_SEL_TOP_PLL0, 12, 1), + MUX(ID_NONE, "mout_bustop_pll_user", mout_bustop_pll_user_p, + MUX_SEL_TOP_PLL0, 8, 1), + MUX(ID_NONE, "mout_memtop_pll_user", mout_memtop_pll_user_p, + MUX_SEL_TOP_PLL0, 4, 1), + MUX(ID_NONE, "mout_mediatop_pll_user", mout_mediatop_pll_user_p, + MUX_SEL_TOP_PLL0, 0, 1), + + + MUX(ID_NONE, "mout_disp_disp_333", mout_disp_disp_333_p, + MUX_SEL_TOP_DISP0, 0, 1), + MUX(ID_NONE, "mout_aclk_disp_333", mout_aclk_disp_333_p, + MUX_SEL_TOP_DISP0, 8, 1), + MUX(ID_NONE, "mout_disp_disp_222", mout_disp_disp_222_p, + MUX_SEL_TOP_DISP0, 12, 1), + MUX(ID_NONE, "mout_aclk_disp_222", mout_aclk_disp_222_p, + MUX_SEL_TOP_DISP0, 20, 1), + MUX(ID_NONE, "mout_disp_media_pixel", mout_disp_media_pixel_p, + MUX_SEL_TOP_DISP1, 8, 1), + MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p, + MUX_SEL_TOP_DISP1, 0, 1), + + MUX(ID_NONE, "mout_sclk_peri_spi0_clk", mout_sclk_peri_spi_clk_p, + MUX_SEL_TOP_PERI1, 8, 1), + MUX(ID_NONE, "mout_sclk_peri_spi1_clk", mout_sclk_peri_spi_clk_p, + MUX_SEL_TOP_PERI1, 4, 1), + MUX(ID_NONE, "mout_sclk_peri_spi2_clk", mout_sclk_peri_spi_clk_p, + MUX_SEL_TOP_PERI1, 0, 1), + MUX(ID_NONE, "mout_sclk_peri_uart0_uclk", mout_sclk_peri_uart_uclk_p, + MUX_SEL_TOP_PERI1, 20, 1), + MUX(ID_NONE, "mout_sclk_peri_uart2_uclk", mout_sclk_peri_uart_uclk_p, + MUX_SEL_TOP_PERI1, 16, 1), + MUX(ID_NONE, "mout_sclk_peri_uart1_uclk", mout_sclk_peri_uart_uclk_p, + MUX_SEL_TOP_PERI1, 12, 1), + + MUX(ID_NONE, "mout_bus4_bustop_100", mout_bus_bustop_100_p, + MUX_SEL_TOP_BUS, 28, 1), + MUX(ID_NONE, "mout_bus4_bustop_400", mout_bus_bustop_400_p, + MUX_SEL_TOP_BUS, 24, 1), + MUX(ID_NONE, "mout_bus3_bustop_100", mout_bus_bustop_100_p, + MUX_SEL_TOP_BUS, 20, 1), + MUX(ID_NONE, "mout_bus3_bustop_400", mout_bus_bustop_400_p, + MUX_SEL_TOP_BUS, 16, 1), + MUX(ID_NONE, "mout_bus2_bustop_400", mout_bus_bustop_400_p, + MUX_SEL_TOP_BUS, 12, 1), + MUX(ID_NONE, "mout_bus2_bustop_100", mout_bus_bustop_100_p, + MUX_SEL_TOP_BUS, 8, 1), + MUX(ID_NONE, "mout_bus1_bustop_100", mout_bus_bustop_100_p, + MUX_SEL_TOP_BUS, 4, 1), + MUX(ID_NONE, "mout_bus1_bustop_400", mout_bus_bustop_400_p, + MUX_SEL_TOP_BUS, 0, 1), + + MUX(ID_NONE, "mout_sclk_fsys_usb", mout_sclk_fsys_usb_p, + MUX_SEL_TOP_FSYS, 0, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc0_sdclkin_a", + mout_sclk_fsys_mmc_sdclkin_a_p, + MUX_SEL_TOP_FSYS, 20, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc1_sdclkin_a", + mout_sclk_fsys_mmc_sdclkin_a_p, + MUX_SEL_TOP_FSYS, 12, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc2_sdclkin_a", + mout_sclk_fsys_mmc_sdclkin_a_p, + MUX_SEL_TOP_FSYS, 4, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc0_sdclkin_b", + mout_sclk_fsys_mmc0_sdclkin_b_p, + MUX_SEL_TOP_FSYS, 24, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc1_sdclkin_b", + mout_sclk_fsys_mmc1_sdclkin_b_p, + MUX_SEL_TOP_FSYS, 16, 1), + MUX(ID_NONE, "mout_sclk_fsys_mmc2_sdclkin_b", + mout_sclk_fsys_mmc2_sdclkin_b_p, + MUX_SEL_TOP_FSYS, 8, 1), + + MUX(ID_NONE, "mout_aclk_isp1_266", mout_aclk_isp1_266_p, + MUX_SEL_TOP_ISP10, 20, 1), + MUX(ID_NONE, "mout_isp1_media_266", mout_isp1_media_266_p, + MUX_SEL_TOP_ISP10, 16, 1), + MUX(ID_NONE, "mout_aclk_isp1_400", mout_aclk_isp1_400_p, + MUX_SEL_TOP_ISP10, 8 , 1), + MUX(ID_NONE, "mout_isp1_media_400", mout_isp1_media_400_p, + MUX_SEL_TOP_ISP10, 4, 1), + + MUX(ID_NONE, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p, + MUX_SEL_TOP_ISP11, 4, 1), + MUX(ID_NONE, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p, + MUX_SEL_TOP_ISP11, 8, 1), + MUX(ID_NONE, "mout_sclk_isp1_uart", mout_sclk_isp_uart_p, + MUX_SEL_TOP_ISP11, 12, 1), + MUX(ID_NONE, "mout_sclk_isp1_sensor2", mout_sclk_isp_sensor_p, + MUX_SEL_TOP_ISP11, 24, 1), + MUX(ID_NONE, "mout_sclk_isp1_sensor1", mout_sclk_isp_sensor_p, + MUX_SEL_TOP_ISP11, 20, 1), + MUX(ID_NONE, "mout_sclk_isp1_sensor0", mout_sclk_isp_sensor_p, + MUX_SEL_TOP_ISP11, 16, 1), + + MUX(ID_NONE, "mout_aclk_mfc_333", mout_aclk_mfc_333_p, + MUX_SEL_TOP_MFC, 8, 1), + MUX(ID_NONE, "mout_mfc_bustop_333", mout_mfc_bustop_333_p, + MUX_SEL_TOP_MFC, 4, 1), + + MUX(ID_NONE, "mout_aclk_g2d_333", mout_aclk_g2d_333_p, + MUX_SEL_TOP_G2D, 8, 1), + MUX(ID_NONE, "mout_g2d_bustop_333", mout_g2d_bustop_333_p, + MUX_SEL_TOP_G2D, 4, 1), + + MUX(ID_NONE, "mout_aclk_gscl_fimc", mout_aclk_gscl_fimc_p, + MUX_SEL_TOP_GSCL, 20, 1), + MUX(ID_NONE, "mout_gscl_bustop_fimc", mout_gscl_bustop_fimc_p, + MUX_SEL_TOP_GSCL, 16, 1), + MUX(ID_NONE, "mout_aclk_gscl_333", mout_aclk_gscl_333_p, + MUX_SEL_TOP_GSCL, 12, 1), + MUX(ID_NONE, "mout_gscl_bustop_333", mout_gscl_bustop_333_p, + MUX_SEL_TOP_GSCL, 8, 1), + MUX(ID_NONE, "mout_aclk_gscl_400", mout_aclk_gscl_400_p, + MUX_SEL_TOP_GSCL, 4, 1), + MUX(ID_NONE, "mout_m2m_mediatop_400", mout_m2m_mediatop_400_p, + MUX_SEL_TOP_GSCL, 0, 1), +}; + +/* DIVIDER CLOCKS */ + +/* + * List of Divider clocks for CMU_AUD +*/ +struct samsung_div_clock exynos5260_aud_div_clks[] __initdata = { + DIV(ID_NONE, "dout_aclk_aud_131", "mout_aud_pll_user", + DIV_AUD0, 0, 4), + DIV(ID_NONE, "dout_sclk_aud_uart", "mout_aud_pll_user", + DIV_AUD1, 12, 4), + DIV(ID_NONE, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm", + DIV_AUD1, 4, 8), + DIV(ID_NONE, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s", + DIV_AUD1, 0, 4), +}; + +/* + * List of Divider clocks for CMU_DISP +*/ +struct samsung_div_clock exynos5260_disp_div_clks[] __initdata = { + DIV(ID_NONE, "dout_sclk_hdmi_phy_pixel_clki", "mout_sclk_hdmi_pixel", + DIV_DISP, 16, 4), + DIV(ID_NONE, "dout_sclk_fimd1_extclkpll", "mout_sclk_disp_pixel_user", + DIV_DISP, 12, 4), + DIV(ID_NONE, "dout_pclk_disp_111", "mout_aclk_disp_222_user", + DIV_DISP, 8, 4), +}; + +/* + * List of Divider clocks for CMU_EGL +*/ +struct samsung_div_clock exynos5260_egl_div_clks[] __initdata = { + DIV(ID_NONE, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3), + DIV(ID_NONE, "dout_egl_pclk_dbg", "dout_egl_atclk", DIV_EGL, 20, 3), + DIV(ID_NONE, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3), + DIV(ID_NONE, "dout_pclk_egl", "dout_egl_atclk", DIV_EGL, 12, 3), + DIV(ID_NONE, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3), + DIV(ID_NONE, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3), + DIV(ID_NONE, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3), +}; + +/* + * List of Divider clocks for CMU_G2D +*/ +struct samsung_div_clock exynos5260_g2d_div_clks[] __initdata = { + DIV(ID_NONE, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user", + DIV_G2D, 0, 3), +}; + +/* + * List of Divider clocks for CMU_G3D +*/ + +struct samsung_div_clock exynos5260_g3d_div_clks[] __initdata = { + DIV(ID_NONE, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3), + DIV(ID_NONE, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3), +}; + +/* + * List of Divider clocks for CMU_GSCL +*/ +struct samsung_div_clock exynos5260_gscl_div_clks[] __initdata = { + DIV(ID_NONE, "dout_aclk_csis_200", "mout_aclk_m2m_400_user", + DIV_GSCL, 4, 3), + DIV(ID_NONE, "dout_pclk_m2m_100", "mout_aclk_m2m_400_user", + DIV_GSCL, 0, 3), +}; + +/* + * List of Divider clocks for CMU_ISP +*/ + +struct samsung_div_clock exynos5260_isp_div_clks[] __initdata = { + DIV(ID_NONE, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2), + DIV(ID_NONE, "dout_ca5_pclkdbg", "mout_kfc", DIV_ISP, 16, 4), + DIV(ID_NONE, "dout_ca5_atclkin", "mout_kfc", DIV_ISP, 12, 3), + DIV(ID_NONE, "dout_pclk_isp_133", "mout_kfc", DIV_ISP, 4, 4), + DIV(ID_NONE, "dout_pclk_isp_66", "mout_kfc", DIV_ISP, 0, 3), +}; + +/* + * List of Divider clocks for CMU_KFC +*/ +struct samsung_div_clock exynos5260_kfc_div_clks[] __initdata = { + DIV(ID_NONE, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3), + DIV(ID_NONE, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3), + DIV(ID_NONE, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3), + DIV(ID_NONE, "dout_kfc_pclk_dbg", "dout_kfc2", DIV_KFC, 12, 3), + DIV(ID_NONE, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3), + DIV(ID_NONE, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3), + DIV(ID_NONE, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3), +}; + +/* + * List of Divider clocks for CMU_MFC +*/ +struct samsung_div_clock exynos5260_mfc_div_clks[] __initdata = { + DIV(ID_NONE, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user", + DIV_MFC, 0, 3), +}; + +/* + * List of Divider clocks for CMU_MIF +*/ +struct samsung_div_clock exynos5260_mif_div_clks[] __initdata = { + DIV(ID_NONE, "dout_aclk_bus_100", "dout_bus_pll", DIV_MIF, 28, 4), + DIV(ID_NONE, "dout_aclk_bus_200", "dout_bus_pll", DIV_MIF, 24, 3), + DIV(ID_NONE, "dout_aclk_mif_466", "dout_clk2x_phy", DIV_MIF, 20, 3), + DIV(ID_NONE, "dout_clk2x_phy", "mout_clk2x_phy", DIV_MIF, 16, 4), + DIV(ID_NONE, "dout_clkm_phy", "mout_clkm_phy", DIV_MIF, 12, 3), + DIV(ID_NONE, "dout_bus_pll", "mout_bus_pll", DIV_MIF, 8, 3), + DIV(ID_NONE, "dout_mem_pll", "mout_mem_pll", DIV_MIF, 4, 3), + DIV(ID_NONE, "dout_media_pll", "mout_media_pll", DIV_MIF, 0, 3), +}; + +/* + * List of Divider clocks for CMU_peri +*/ +struct samsung_div_clock exynos5260_peri_div_clks[] __initdata = { + DIV(ID_NONE, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 0, 6), + DIV(ID_NONE, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8), +}; + +/* + * List of Divider clocks for CMU_TOP +*/ +struct samsung_div_clock exynos5260_top_div_clks[] __initdata = { + DIV(ID_NONE, "dout_aclk_mfc_333", "mout_aclk_mfc_333", + DIV_TOP_G2D_MFC, 4, 3), + + DIV(ID_NONE, "dout_aclk_g2d_333", "mout_aclk_g2d_333", + DIV_TOP_GSCL_ISP0, 0, 3), + + DIV(ID_NONE, "dout_sclk_isp1_sensor2_a", "mout_aclk_gscl_fimc", + DIV_TOP_GSCL_ISP0, 24, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor1_a", "mout_aclk_gscl_400", + DIV_TOP_GSCL_ISP0, 20, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor0_a", "mout_aclk_gscl_fimc", + DIV_TOP_GSCL_ISP0, 16, 4), + DIV(ID_NONE, "dout_aclk_gscl_fimc", "mout_aclk_gscl_fimc", + DIV_TOP_GSCL_ISP0, 8, 3), + DIV(ID_NONE, "dout_aclk_gscl_400", "mout_aclk_gscl_400", + DIV_TOP_GSCL_ISP0, 4, 3), + DIV(ID_NONE, "dout_aclk_gscl_333", "mout_aclk_gscl_333", + DIV_TOP_GSCL_ISP0, 0, 3), + + DIV(ID_NONE, "dout_sclk_isp1_spi0_b", "dout_sclk_isp1_spi0_a", + DIV_TOP_ISP10, 16, 8), + DIV(ID_NONE, "dout_sclk_isp1_spi0_a", "mout_sclk_isp1_spi0", + DIV_TOP_ISP10, 12, 4), + DIV(ID_NONE, "dout_aclk_isp1_400", "mout_aclk_isp1_400", + DIV_TOP_ISP10, 4, 3), + DIV(ID_NONE, "dout_aclk_isp1_266", "mout_aclk_isp1_266", + DIV_TOP_ISP10, 0, 3), + DIV(ID_NONE, "dout_sclk_isp1_uart", "mout_sclk_isp1_uart", + DIV_TOP_ISP11, 12, 4), + DIV(ID_NONE, "dout_sclk_isp1_spi1_b", "dout_sclk_isp1_spi1_a", + DIV_TOP_ISP11, 4, 8), + DIV(ID_NONE, "dout_sclk_isp1_spi1_a", "mout_sclk_isp1_spi1", + DIV_TOP_ISP11, 0, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor2_b", "dout_sclk_isp1_sensor2_a", + DIV_TOP_ISP11, 24, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor1_b", "dout_sclk_isp1_sensor1_a", + DIV_TOP_ISP11, 20, 4), + DIV(ID_NONE, "dout_sclk_isp1_sensor0_b", "dout_sclk_isp1_sensor0_a", + DIV_TOP_ISP11, 16, 4), + + DIV(ID_NONE, "dout_sclk_hpm_targetclk", "mout_bustop_pll_user", + DIV_TOP_HPM, 0, 3), + + DIV(ID_NONE, "dout_sclk_disp_pixel", "mout_sclk_disp_pixel", + DIV_TOP_DISP, 8, 3), + DIV(ID_NONE, "dout_aclk_disp_222", "mout_aclk_disp_222", + DIV_TOP_DISP, 4, 3), + DIV(ID_NONE, "dout_aclk_disp_333", "mout_aclk_disp_333", + DIV_TOP_DISP, 0, 3), + + DIV(ID_NONE, "dout_aclk_bus4_100", "mout_bus4_bustop_100", + DIV_TOP_BUS, 28, 4), + DIV(ID_NONE, "dout_aclk_bus4_400", "mout_bus4_bustop_400", + DIV_TOP_BUS, 24, 3), + DIV(ID_NONE, "dout_aclk_bus3_100", "mout_bus3_bustop_100", + DIV_TOP_BUS, 20, 4), + DIV(ID_NONE, "dout_aclk_bus3_400", "mout_bus3_bustop_400", + DIV_TOP_BUS, 16, 3), + DIV(ID_NONE, "dout_aclk_bus2_100", "mout_bus2_bustop_100", + DIV_TOP_BUS, 12, 4), + DIV(ID_NONE, "dout_aclk_bus2_400", "mout_bus2_bustop_400", + DIV_TOP_BUS, 8, 3), + DIV(ID_NONE, "dout_aclk_bus1_100", "mout_bus1_bustop_100", + DIV_TOP_BUS, 4, 4), + DIV(ID_NONE, "dout_aclk_bus1_400", "mout_bus1_bustop_400", + DIV_TOP_BUS, 0, 3), + + DIV(ID_NONE, "dout_sclk_peri_spi1_b", "dout_sclk_peri_spi1_a", + DIV_TOP_PERI0, 20, 8), + DIV(ID_NONE, "dout_sclk_peri_spi1_a", "mout_sclk_peri_spi1_clk", + DIV_TOP_PERI0, 16, 4), + DIV(ID_NONE, "dout_sclk_peri_spi0_b", "dout_sclk_peri_spi0_a", + DIV_TOP_PERI0, 8, 8), + DIV(ID_NONE, "dout_sclk_peri_spi0_a", "mout_sclk_peri_spi0_clk", + DIV_TOP_PERI0, 4, 4), + DIV(ID_NONE, "dout_sclk_peri_uart0", "mout_sclk_peri_uart0_uclk", + DIV_TOP_PERI1, 24, 4), + DIV(ID_NONE, "dout_sclk_peri_uart2", "mout_sclk_peri_uart2_uclk", + DIV_TOP_PERI1, 20, 4), + DIV(ID_NONE, "dout_sclk_peri_uart1", "mout_sclk_peri_uart1_uclk", + DIV_TOP_PERI1, 16, 4), + DIV(ID_NONE, "dout_sclk_peri_spi2_b", "dout_sclk_peri_spi2_a", + DIV_TOP_PERI1, 4, 8), + DIV(ID_NONE, "dout_sclk_peri_spi2_a", "mout_sclk_peri_spi2_clk", + DIV_TOP_PERI1, 0, 4), + DIV(ID_NONE, "dout_aclk_peri_aud", "mout_audtop_pll_user", + DIV_TOP_PERI2, 24, 3), + DIV(ID_NONE, "dout_aclk_peri_66", "mout_bustop_pll_user", + DIV_TOP_PERI2, 20, 4), + + DIV(ID_NONE, "dout_sclk_fsys_mmc0_sdclkin_b", + "dout_sclk_fsys_mmc0_sdclkin_a", + DIV_TOP_FSYS0, 16, 8), + DIV(ID_NONE, "dout_sclk_fsys_mmc0_sdclkin_a", + "mout_sclk_fsys_mmc0_sdclkin_b", + DIV_TOP_FSYS0, 12, 4), + DIV(ID_NONE, "dout_sclk_fsys_usbdrd30_suspend_clk", + "mout_sclk_fsys_usb", + DIV_TOP_FSYS0, 4, 4), + DIV(ID_NONE, "dout_aclk_fsys_200", "mout_bustop_pll_user", + DIV_TOP_FSYS0, 0, 3), + + DIV(ID_NONE, "dout_sclk_fsys_mmc2_sdclkin_b", + "dout_sclk_fsys_mmc2_sdclkin_a", + DIV_TOP_FSYS1, 16, 8), + DIV(ID_NONE, "dout_sclk_fsys_mmc2_sdclkin_a", + "mout_sclk_fsys_mmc2_sdclkin_b", + DIV_TOP_FSYS1, 12, 4), + DIV(ID_NONE, "dout_sclk_fsys_mmc1_sdclkin_b", + "dout_sclk_fsys_mmc1_sdclkin_a", + DIV_TOP_FSYS1, 4, 8), + DIV(ID_NONE, "dout_sclk_fsys_mmc1_sdclkin_a", + "mout_sclk_fsys_mmc1_sdclkin_b", + DIV_TOP_FSYS1, 0, 4), +}; + +/* GATE CLOCKS */ + +/* + * List of Gate clocks for CMU_AUD +*/ +struct samsung_gate_clock exynos5260_aud_gate_clks[] __initdata = { + GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131", + EN_IP_AUD, 4, 0, 0), + GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0), + GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0), + GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131", + EN_IP_AUD, 1, 0, 0), + GATE(ID_NONE, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD, 0, 0, 0), + + GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart", + EN_SCLK_AUD, 2, 0, 0), + GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm", + EN_SCLK_AUD, 1, 0, 0), + GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s", + EN_SCLK_AUD, 0, 0, 0), +}; + +/* + * List of Gate clocks for CMU_DISP +*/ +struct samsung_gate_clock exynos5260_disp_gate_clks[] __initdata = { + GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user", + EN_IP_DISP, 25, 0, 0), + GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1", + "mout_aclk_disp_222_user", + EN_IP_DISP, 23, 0, 0), + GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0", + "mout_aclk_disp_222_user", + EN_IP_DISP, 22, 0, 0), + GATE(ID_NONE, "clk_pixel_mixer", "mout_aclk_disp_222_user", + EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "clk_pixel_disp", "mout_aclk_disp_222_user", + EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0), + GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user", + EN_IP_DISP, 11, 0, 0), + GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user", + EN_IP_DISP, 10, 0, 0), + GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user", + EN_IP_DISP, 9, 0, 0), + GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user", + EN_IP_DISP, 8, 0, 0), + GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user", + EN_IP_DISP, 7, 0, 0), + GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user", + EN_IP_DISP, 6, 0, 0), + GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user", + EN_IP_DISP, 5, 0, 0), + GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user", + EN_IP_DISP, 4, 0, 0), + + GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki", + "dout_sclk_hdmi_phy_pixel_clki", + EN_SCLK_DISP0, 29, 0, 0), + GATE(DISP_SCLK_HDMI, "sclk_hdmi_link_i_pixel", + "mout_phyclk_hdmi_phy_pixel_clko_user", + EN_SCLK_DISP0, 26, 0, 0), +}; + +/* + * List of Gate clocks for CMU_EGL +*/ +struct samsung_gate_clock exynos5260_egl_gate_clks[] __initdata = { +}; + +/* + * List of Gate clocks for CMU_FSYS +*/ +struct samsung_gate_clock exynos5260_fsys_gate_clks[] __initdata = { + GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200", + EN_IP_FSYS, 20, 0, 0), + GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200", + EN_IP_FSYS, 18, 0, 0), + GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200", + EN_IP_FSYS, 15, 0, 0), + GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200", + EN_IP_FSYS, 14, 0, 0), + GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200", + EN_IP_FSYS, 13, 0, 0), + GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200", + EN_IP_FSYS, 9, 0, 0), + GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200", + EN_IP_FSYS, 8, 0, 0), + GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200", + EN_IP_FSYS, 7, 0, 0), + GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200", + EN_IP_FSYS, 6, 0, 0), + + GATE(FSYS_CLK_RTIC, "clk_rtic", "mout_bustop_pll_user", + EN_IP_FSYS_SECURE_RTIC, 11, 0, 0), + GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "mout_bustop_pll_user", + EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0), + + + GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g", + "mout_phyclk_usbdrd30_phyclock_user", + EN_SCLK_FSYS, 7, 0, 0), + GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock", + "mout_phyclk_usbdrd30_phyclock_user", + EN_SCLK_FSYS, 1, 0, 0), +}; + +/* + * List of Gate clocks for CMU_G2D +*/ +struct samsung_gate_clock exynos5260_g2d_gate_clks[] __initdata = { + GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user", + EN_IP_G2D, 16, 0, 0), + GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user", + EN_IP_G2D, 6, 0, 0), + GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user", + EN_IP_G2D, 5, 0, 0), + GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user", + EN_IP_G2D, 4, 0, 0), + + GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user", + EN_IP_G2D_SECURE_SSS, 17, 0, 0), + GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user", + EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0), + GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss", + "mout_aclk_g2d_333_user", + EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0), + GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user", + EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0), + GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user", + EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0), + GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user", + EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0), +}; + +/* + * List of Gate clocks for CMU_G3D +*/ +struct samsung_gate_clock exynos5260_g3d_gate_clks[] __initdata = { + GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d", + EN_IP_G3D, 3, 0, 0), + GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0), +}; + +/* + * List of Gate clocks for CMU_GSCL +*/ +struct samsung_gate_clock exynos5260_gscl_gate_clks[] __initdata = { + GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1", "mout_aclk_gscl_333", + EN_IP_GSCL, 9, 0, 0), + GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0", "mout_aclk_gscl_333", + EN_IP_GSCL, 8, 0, 0), + GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333", + EN_IP_GSCL, 5, 0, 0), + GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333", + EN_IP_GSCL, 4, 0, 0), + GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333", + EN_IP_GSCL, 3, 0, 0), + GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333", + EN_IP_GSCL, 2, 0, 0), + GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d", + "mout_aclk_gscl_fimc_user", + EN_IP_GSCL_FIMC, 12, 0, 0), + GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b", + "mout_aclk_gscl_fimc_user", + EN_IP_GSCL_FIMC, 11, 0, 0), + GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a", + "mout_aclk_gscl_fimc_user", + EN_IP_GSCL_FIMC, 10, 0, 0), + GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user", + EN_IP_GSCL_FIMC, 9, 0, 0), + GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user", + EN_IP_GSCL_FIMC, 8, 0, 0), + GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d", + "mout_aclk_gscl_fimc_user", + EN_IP_GSCL_FIMC, 7, 0, 0), + GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b", + "mout_aclk_gscl_fimc_user", + EN_IP_GSCL_FIMC, 6, 0, 0), + GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a", + "mout_aclk_gscl_fimc_user", + EN_IP_GSCL_FIMC, 5, 0, 0), + GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0", + "mout_aclk_gscl_333", + EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0), + GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333", + EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0), + GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0", + "mout_aclk_m2m_400_user", + EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0), + GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1", + "mout_aclk_m2m_400_user", + EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0), + + GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200", + EN_SCLK_GSCL_FIMC, 1, 0, 0), + GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200", + EN_SCLK_GSCL_FIMC, 0, 0, 0), +}; + +/* + * List of Gate clocks for CMU_ISP +*/ +struct samsung_gate_clock exynos5260_isp_gate_clks[] __initdata = { + GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266", + EN_IP_ISP0, 15, 0, 0), + + GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266", + EN_IP_ISP1, 31, 0, 0), + GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266", + EN_IP_ISP1, 30, 0, 0), + GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266", + EN_IP_ISP1, 28, 0, 0), + GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266", + EN_IP_ISP1, 27, 0, 0), + + GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp", + "mout_aclk_isp1_266", + EN_IP_ISP1, 26, 0, 0), + GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc", + "mout_aclk_isp1_266", + EN_IP_ISP1, 25, 0, 0), + GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266", + EN_IP_ISP1, 24, 0, 0), + GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266", + EN_IP_ISP1, 23, 0, 0), + GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266", + EN_IP_ISP1, 22, 0, 0), + GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266", + EN_IP_ISP1, 21, 0, 0), + GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266", + EN_IP_ISP1, 14, 0, 0), + GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266", + EN_IP_ISP1, 11, 0, 0), + GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266", + EN_IP_ISP1, 10, 0, 0), + GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266", + EN_IP_ISP1, 9, 0, 0), + GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266", + EN_IP_ISP1, 8, 0, 0), + GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266", + EN_IP_ISP1, 7, 0, 0), + GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp", + "mout_aclk_isp1_266", + EN_IP_ISP1, 6, 0, 0), + GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc", + "mout_aclk_isp1_266", + EN_IP_ISP1, 5, 0, 0), + GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266", + EN_IP_ISP1, 4, 0, 0), + GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266", + EN_IP_ISP1, 3, 0, 0), + GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266", + EN_IP_ISP1, 2, 0, 0), + GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266", + EN_IP_ISP1, 1, 0, 0), + + GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll", + EN_SCLK_ISP, 9, 0, 0), + GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll", + EN_SCLK_ISP, 8, 0, 0), + GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll", + EN_SCLK_ISP, 7, 0, 0), +}; + +/* + * List of Gate clocks for CMU_KFC +*/ +struct samsung_gate_clock exynos5260_kfc_gate_clks[] __initdata = { +}; + +/* + * List of Gate clocks for CMU_MFC +*/ +struct samsung_gate_clock exynos5260_mfc_gate_clks[] __initdata = { + GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user", + EN_IP_MFC, 1, 0, 0), + + GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user", + EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0), + GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user", + EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0), +}; + +/* + * List of Gate clocks for CMU_MIF +*/ +struct samsung_gate_clock exynos5260_mif_gate_clks[] __initdata = { + GATE(ID_NONE, "clk_lpddr3phy_wrap1", "dout_clk2x_phy", + EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "clk_lpddr3phy_wrap0", "dout_clk2x_phy", + EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "clk_monocnt", "dout_aclk_bus_100", + EN_IP_MIF_SECURE_MONOCNT, 22, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "clk_mif_rtc", "dout_aclk_bus_100", + EN_IP_MIF_SECURE_RTC_APBIF, 23, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "clk_drex1", "dout_aclk_mif_466", + EN_IP_MIF_SECURE_DREX1_TZ, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "clk_drex0", "dout_aclk_mif_466", + EN_IP_MIF_SECURE_DREX0_TZ, 9, + CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "clk_intmem", "dout_aclk_bus_200", + EN_IP_MIF_SECURE_INTEMEM, 11, + CLK_IGNORE_UNUSED, 0), + + GATE(ID_NONE, "sclk_lpddr3phy_wrap_u1", "dout_clkm_phy", + EN_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), + GATE(ID_NONE, "sclk_lpddr3phy_wrap_u0", "dout_clkm_phy", + EN_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), +}; + +/* + * List of Gate clocks for CMU_PERI +*/ +struct samsung_gate_clock exynos5260_peri_gate_clks[] __initdata = { + GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66", + EN_IP_PERI0, 25, 0, 0), + GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66", + EN_IP_PERI0, 24, 0, 0), + GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66", + EN_IP_PERI0, 23, 0, 0), + GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66", + EN_IP_PERI0, 22, 0, 0), + GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66", + EN_IP_PERI0, 21, 0, 0), + GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66", + EN_IP_PERI0, 20, 0, 0), + GATE(PERI_CLK_PCM, "clk_pcm", "dout_aclk_peri_66", + EN_IP_PERI0, 18, 0, 0), + GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66", + EN_IP_PERI0, 17, 0, 0), + GATE(PERI_CLK_I2S, "clk_i2s", "dout_aclk_peri_66", + EN_IP_PERI0, 16, 0, 0), + GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66", + EN_IP_PERI0, 15, 0, 0), + GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66", + EN_IP_PERI0, 14, 0, 0), + GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66", + EN_IP_PERI0, 13, 0, 0), + GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66", + EN_IP_PERI0, 12, 0, 0), + GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66", + EN_IP_PERI0, 11, 0, 0), + GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66", + EN_IP_PERI0, 10, 0, 0), + GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66", + EN_IP_PERI0, 9, 0, 0), + GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66", + EN_IP_PERI0, 8, 0, 0), + GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66", + EN_IP_PERI0, 7, 0, 0), + GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66", + EN_IP_PERI0, 6, 0, 0), + GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66", + EN_IP_PERI0, 5, 0, 0), + GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66", + EN_IP_PERI0, 1, 0, 0), + + GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66", + EN_IP_PERI2, 21, 0, 0), + GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66", + EN_IP_PERI2, 20, 0, 0), + GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66", + EN_IP_PERI2, 19, 0, 0), + GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66", + EN_IP_PERI2, 18, 0, 0), + GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66", + EN_IP_PERI2, 14, 0, 0), + GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66", + EN_IP_PERI2, 13, 0, 0), + GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66", + EN_IP_PERI2, 12, 0, 0), + GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66", + EN_IP_PERI2, 11, 0, 0), + GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66", + EN_IP_PERI2, 10, 0, 0), + GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66", + EN_IP_PERI2, 9, 0, 0), + GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66", + EN_IP_PERI2, 8, 0, 0), + GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66", + EN_IP_PERI2, 7, 0, 0), + GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66", + EN_IP_PERI2, 6, 0, 0), + GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66", + EN_IP_PERI2, 3, 0, 0), + GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66", + EN_IP_PERI2, 0, 0, 0), + + GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_CHIPID, 2, 0, 0), + GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0), + GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0), + GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_SECKEY, 5, 0, 0), + GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0), + + GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_TZPC, 20, 0, 0), + GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_TZPC, 19, 0, 0), + GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_TZPC, 18, 0, 0), + GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_TZPC, 17, 0, 0), + GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_TZPC, 16, 0, 0), + GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_TZPC, 15, 0, 0), + GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_TZPC, 14, 0, 0), + GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_TZPC, 13, 0, 0), + GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_TZPC, 12, 0, 0), + GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_TZPC, 11, 0, 0), + GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66", + EN_IP_PERI_SECURE_TZPC, 10, 0, 0), + + GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2", + EN_SCLK_PERI, 12, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1", + EN_SCLK_PERI, 11, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0", + EN_SCLK_PERI, 10, CLK_IGNORE_UNUSED, 0), + GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b", + EN_SCLK_PERI, 9, 0, 0), + GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b", + EN_SCLK_PERI, 8, 0, 0), + GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b", + EN_SCLK_PERI, 7, 0, 0), + GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b", + EN_SCLK_PERI, 2, 0, 0), + GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1, 0, 0), + GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0, 0, 0), +}; + +/* + * List of Gate clocks for CMU_TOP +*/ +struct samsung_gate_clock exynos5260_top_gate_clks[] __initdata = { + GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel", + EN_ACLK_TOP, 10, 0, 0), + GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin", + "dout_sclk_fsys_mmc2_sdclkin_b", + EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0), + GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin", + "dout_sclk_fsys_mmc1_sdclkin_b", + EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT, + 0), + GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin", + "dout_sclk_fsys_mmc0_sdclkin_b", + EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0), +}; + +/* +* Applicable for all 2550 Type PLLS for Exynos5260, listed below +* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, +* BUS_PLL, MEDIA_PLL, G3D_PLL. +*/ +static const struct samsung_pll_rate_table exynos5260_pll2550_24mhz_tbl[] = { + PLL_35XX_RATE(1700000000, 425, 6, 0), + PLL_35XX_RATE(1600000000, 200, 3, 0), + PLL_35XX_RATE(1500000000, 250, 4, 0), + PLL_35XX_RATE(1400000000, 175, 3, 0), + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 400, 4, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(933000000, 311, 4, 1), + PLL_35XX_RATE(900000000, 300, 4, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(733000000, 733, 12, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(667000000, 667, 12, 1), + PLL_35XX_RATE(633000000, 211, 4, 1), + PLL_35XX_RATE(620000000, 310, 3, 2), + PLL_35XX_RATE(600000000, 400, 4, 2), + PLL_35XX_RATE(543000000, 362, 4, 2), + PLL_35XX_RATE(533000000, 533, 6, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(450000000, 300, 4, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(350000000, 175, 3, 2), + PLL_35XX_RATE(300000000, 400, 4, 3), + PLL_35XX_RATE(266000000, 266, 3, 3), + PLL_35XX_RATE(200000000, 200, 3, 3), + PLL_35XX_RATE(160000000, 160, 3, 3), +}; + +/* +* Applicable for 2650 Type PLL for AUD_PLL. +*/ +static const struct samsung_pll_rate_table exynos5260_pll2650_24mhz_tbl[] = { + PLL_36XX_RATE(1600000000, 200, 3, 0, 0), + PLL_36XX_RATE(1200000000, 100, 2, 0, 0), + PLL_36XX_RATE(1000000000, 250, 3, 1, 0), + PLL_36XX_RATE(800000000, 200, 3, 1, 0), + PLL_36XX_RATE(600000000, 100, 2, 1, 0), + PLL_36XX_RATE(532000000, 266, 3, 2, 0), + PLL_36XX_RATE(480000000, 160, 2, 2, 0), + PLL_36XX_RATE(432000000, 144, 2, 2, 0), + PLL_36XX_RATE(400000000, 200, 3, 2, 0), + PLL_36XX_RATE(394216000, 459, 7, 2, 49282), + PLL_36XX_RATE(333000000, 111, 2, 2, 0), + PLL_36XX_RATE(300000000, 100, 2, 2, 0), + PLL_36XX_RATE(266000000, 266, 3, 3, 0), + PLL_36XX_RATE(200000000, 200, 3, 3, 0), + PLL_36XX_RATE(166000000, 166, 3, 3, 0), + PLL_36XX_RATE(133000000, 266, 3, 4, 0), + PLL_36XX_RATE(100000000, 200, 3, 4, 0), + PLL_36XX_RATE(66000000, 176, 2, 5, 0), +}; + +static struct samsung_pll_clock exynos5260_top_pll_clks[] __initdata = { + PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll", + DISP_PLL_LOCK, DISP_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), + PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", + AUD_PLL_LOCK, AUD_PLL_CON0, + exynos5260_pll2650_24mhz_tbl), +}; + +static struct samsung_pll_clock exynos5260_egl_pll_clks[] __initdata = { + PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll", + EGL_PLL_LOCK, EGL_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), +}; + +static struct samsung_pll_clock exynos5260_kfc_pll_clks[] __initdata = { + PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll", + KFC_PLL_LOCK, KFC_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), +}; + +static struct samsung_pll_clock exynos5260_mif_pll_clks[] __initdata = { + PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll", + MEM_PLL_LOCK, MEM_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), + PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll", + BUS_PLL_LOCK, BUS_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), + PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll", + MEDIA_PLL_LOCK, MEDIA_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), +}; + +static struct samsung_pll_clock exynos5260_g3d_pll_clks[] __initdata = { + PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll", + G3D_PLL_LOCK, G3D_PLL_CON0, + exynos5260_pll2550_24mhz_tbl), +}; + +void __init exynos5260_clk_aud_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + rdump = exynos5260_aud_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_aud_clk_regs); + + ctx = samsung_clk_init(np, reg_base, AUD_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_aud_mux_clks, + ARRAY_SIZE(exynos5260_aud_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_aud_div_clks, + ARRAY_SIZE(exynos5260_aud_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_aud_gate_clks, + ARRAY_SIZE(exynos5260_aud_gate_clks)); + + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +void __init exynos5260_clk_disp_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + rdump = exynos5260_disp_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_disp_clk_regs); + + ctx = samsung_clk_init(np, reg_base, DISP_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_disp_mux_clks, + ARRAY_SIZE(exynos5260_disp_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_disp_div_clks, + ARRAY_SIZE(exynos5260_disp_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_disp_gate_clks, + ARRAY_SIZE(exynos5260_disp_gate_clks)); + + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +void __init exynos5260_clk_egl_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + rdump = exynos5260_egl_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_egl_clk_regs); + + ctx = samsung_clk_init(np, reg_base, EGL_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_pll(ctx, exynos5260_egl_pll_clks, + ARRAY_SIZE(exynos5260_egl_pll_clks), + reg_base); + + samsung_clk_register_mux(ctx, exynos5260_egl_mux_clks, + ARRAY_SIZE(exynos5260_egl_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_egl_div_clks, + ARRAY_SIZE(exynos5260_egl_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_egl_gate_clks, + ARRAY_SIZE(exynos5260_egl_gate_clks)); + + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +void __init exynos5260_clk_fsys_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + rdump = exynos5260_fsys_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_fsys_clk_regs); + + ctx = samsung_clk_init(np, reg_base, FSYS_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_fsys_mux_clks, + ARRAY_SIZE(exynos5260_fsys_mux_clks)); + samsung_clk_register_gate(ctx, exynos5260_fsys_gate_clks, + ARRAY_SIZE(exynos5260_fsys_gate_clks)); + + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +void __init exynos5260_clk_g2d_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + rdump = exynos5260_g2d_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_g2d_clk_regs); + + ctx = samsung_clk_init(np, reg_base, G2D_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_g2d_mux_clks, + ARRAY_SIZE(exynos5260_g2d_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_g2d_div_clks, + ARRAY_SIZE(exynos5260_g2d_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_g2d_gate_clks, + ARRAY_SIZE(exynos5260_g2d_gate_clks)); + + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +void __init exynos5260_clk_g3d_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + rdump = exynos5260_g3d_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_g3d_clk_regs); + + ctx = samsung_clk_init(np, reg_base, G3D_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + samsung_clk_register_pll(ctx, exynos5260_g3d_pll_clks, + ARRAY_SIZE(exynos5260_g3d_pll_clks), + reg_base); + samsung_clk_register_mux(ctx, exynos5260_g3d_mux_clks, + ARRAY_SIZE(exynos5260_g3d_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_g3d_div_clks, + ARRAY_SIZE(exynos5260_g3d_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_g3d_gate_clks, + ARRAY_SIZE(exynos5260_g3d_gate_clks)); + + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +void __init exynos5260_clk_gscl_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + rdump = exynos5260_gscl_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_gscl_clk_regs); + + ctx = samsung_clk_init(np, reg_base, GSCL_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_gscl_mux_clks, + ARRAY_SIZE(exynos5260_gscl_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_gscl_div_clks, + ARRAY_SIZE(exynos5260_gscl_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_gscl_gate_clks, + ARRAY_SIZE(exynos5260_gscl_gate_clks)); + + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +void __init exynos5260_clk_isp_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + rdump = exynos5260_isp_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_isp_clk_regs); + + ctx = samsung_clk_init(np, reg_base, ISP_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_isp_mux_clks, + ARRAY_SIZE(exynos5260_isp_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_isp_div_clks, + ARRAY_SIZE(exynos5260_isp_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_isp_gate_clks, + ARRAY_SIZE(exynos5260_isp_gate_clks)); + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +void __init exynos5260_clk_kfc_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + rdump = exynos5260_kfc_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_kfc_clk_regs); + + ctx = samsung_clk_init(np, reg_base, KFC_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_pll(ctx, exynos5260_kfc_pll_clks, + ARRAY_SIZE(exynos5260_kfc_pll_clks), + reg_base); + samsung_clk_register_mux(ctx, exynos5260_kfc_mux_clks, + ARRAY_SIZE(exynos5260_kfc_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_kfc_div_clks, + ARRAY_SIZE(exynos5260_kfc_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_kfc_gate_clks, + ARRAY_SIZE(exynos5260_kfc_gate_clks)); + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +void __init exynos5260_clk_mfc_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + rdump = exynos5260_mfc_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_mfc_clk_regs); + + ctx = samsung_clk_init(np, reg_base, MFC_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_mfc_mux_clks, + ARRAY_SIZE(exynos5260_mfc_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_mfc_div_clks, + ARRAY_SIZE(exynos5260_mfc_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_mfc_gate_clks, + ARRAY_SIZE(exynos5260_mfc_gate_clks)); + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +void __init exynos5260_clk_mif_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + rdump = exynos5260_mif_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_mif_clk_regs); + + ctx = samsung_clk_init(np, reg_base, MIF_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_pll(ctx, exynos5260_mif_pll_clks, + ARRAY_SIZE(exynos5260_mif_pll_clks), + reg_base); + samsung_clk_register_mux(ctx, exynos5260_mif_mux_clks, + ARRAY_SIZE(exynos5260_mif_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_mif_div_clks, + ARRAY_SIZE(exynos5260_mif_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_mif_gate_clks, + ARRAY_SIZE(exynos5260_mif_gate_clks)); + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +void __init exynos5260_clk_peri_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + rdump = exynos5260_peri_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_peri_clk_regs); + + ctx = samsung_clk_init(np, reg_base, PERI_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_mux(ctx, exynos5260_peri_mux_clks, + ARRAY_SIZE(exynos5260_peri_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_peri_div_clks, + ARRAY_SIZE(exynos5260_peri_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_peri_gate_clks, + ARRAY_SIZE(exynos5260_peri_gate_clks)); + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +void __init exynos5260_clk_top_init(struct device_node *np) +{ + void __iomem *reg_base; + static unsigned long *rdump; + struct samsung_clk_provider *ctx; + unsigned long nr_rdump; + + if (!np) + panic("%s: unable to determine cmu\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + rdump = exynos5260_top_clk_regs; + nr_rdump = ARRAY_SIZE(exynos5260_top_clk_regs); + + ctx = samsung_clk_init(np, reg_base, TOP_NR_CLK); + if (!ctx) + panic("%s: unable to alllocate ctx\n", __func__); + + samsung_clk_register_fixed_rate(ctx, + exynos5260_fixed_rate_ext_clks, + ARRAY_SIZE( + exynos5260_fixed_rate_ext_clks)); + + samsung_clk_register_fixed_rate(ctx, + exynos5260_fixed_rate_clks, + ARRAY_SIZE(exynos5260_fixed_rate_clks)); + + samsung_clk_register_pll(ctx, exynos5260_top_pll_clks, + ARRAY_SIZE(exynos5260_top_pll_clks), + reg_base); + + samsung_clk_register_mux(ctx, exynos5260_top_mux_clks, + ARRAY_SIZE(exynos5260_top_mux_clks)); + samsung_clk_register_div(ctx, exynos5260_top_div_clks, + ARRAY_SIZE(exynos5260_top_div_clks)); + samsung_clk_register_gate(ctx, exynos5260_top_gate_clks, + ARRAY_SIZE(exynos5260_top_gate_clks)); + + exynos5260_clk_sleep_init(reg_base, rdump, nr_rdump); +} + +struct of_device_id __clk_of_table_exynos5260[] + __used __section(__clk_of_table) = { + { + .compatible = "samsung,exynos5260-clock-top", + .data = exynos5260_clk_top_init, + }, { + .compatible = "samsung,exynos5260-clock-peri", + .data = exynos5260_clk_peri_init, + }, { + .compatible = "samsung,exynos5260-clock-egl", + .data = exynos5260_clk_egl_init, + }, { + .compatible = "samsung,exynos5260-clock-kfc", + .data = exynos5260_clk_kfc_init, + }, { + .compatible = "samsung,exynos5260-clock-g2d", + .data = exynos5260_clk_g2d_init, + }, { + .compatible = "samsung,exynos5260-clock-mif", + .data = exynos5260_clk_mif_init, + }, { + .compatible = "samsung,exynos5260-clock-mfc", + .data = exynos5260_clk_mfc_init, + }, { + .compatible = "samsung,exynos5260-clock-g3d", + .data = exynos5260_clk_g3d_init, + }, { + .compatible = "samsung,exynos5260-clock-fsys", + .data = exynos5260_clk_fsys_init, + }, { + .compatible = "samsung,exynos5260-clock-aud", + .data = exynos5260_clk_aud_init, + }, { + .compatible = "samsung,exynos5260-clock-isp", + .data = exynos5260_clk_isp_init, + }, { + .compatible = "samsung,exynos5260-clock-gscl", + .data = exynos5260_clk_gscl_init, + }, { + .compatible = "samsung,exynos5260-clock-disp", + .data = exynos5260_clk_disp_init, + }, { + }, +}; diff --git a/drivers/clk/samsung/clk-exynos5260.h b/drivers/clk/samsung/clk-exynos5260.h new file mode 100644 index 0000000..392c152 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos5260.h @@ -0,0 +1,480 @@ +#ifndef __CLK_EXYNOS5260_H +#define __CLK_EXYNOS5260_H + +/* +*Base address for different CMUs +*TODO: All Bases should be removed at earliest. +*/ +#define CMU_AUD_BASE 0x128C0000 +#define CMU_DISP_BASE 0x14550000 +#define CMU_EGL_BASE 0x10600000 +#define CMU_FSYS_BASE 0x122E0000 +#define CMU_G2D_BASE 0x10A00000 +#define CMU_G3D_BASE 0x11830000 +#define CMU_GSCL_BASE 0x13F00000 +#define CMU_ISP_BASE 0x133C0000 +#define CMU_KFC_BASE 0x10700000 +#define CMU_MFC_BASE 0x11090000 +#define CMU_MIF_BASE 0x10CE0000 +#define CMU_PERI_BASE 0x10200000 +#define CMU_TOP_BASE 0x10010000 + +#define AUD_REG(x) (x) +#define DISP_REG(x) (x) +#define EGL_REG(x) (x) +#define FSYS_REG(x) (x) +#define G2D_REG(x) (x) +#define G3D_REG(x) (x) +#define GSCL_REG(x) (x) +#define ISP_REG(x) (x) +#define KFC_REG(x) (x) +#define MFC_REG(x) (x) +#define MIF_REG(x) (x) +#define PERI_REG(x) (x) +#define TOP_REG(x) (x) + +/* +*Registers for CMU_AUD +*/ +#define MUX_SEL_AUD AUD_REG(0x0200) +#define MUX_ENABLE_AUD AUD_REG(0x0300) +#define MUX_STAT_AUD AUD_REG(0x0400) +#define MUX_IGNORE_AUD AUD_REG(0x0500) +#define DIV_AUD0 AUD_REG(0x0600) +#define DIV_AUD1 AUD_REG(0x0604) +#define DIV_STAT_AUD0 AUD_REG(0x0700) +#define DIV_STAT_AUD1 AUD_REG(0x0704) +#define EN_ACLK_AUD AUD_REG(0x0800) +#define EN_PCLK_AUD AUD_REG(0x0900) +#define EN_SCLK_AUD AUD_REG(0x0a00) +#define EN_IP_AUD AUD_REG(0x0b00) + +/* +*Registers for CMU_DISP +*/ +#define MUX_SEL_DISP0 DISP_REG(0x0200) +#define MUX_SEL_DISP1 DISP_REG(0x0204) +#define MUX_SEL_DISP2 DISP_REG(0x0208) +#define MUX_SEL_DISP3 DISP_REG(0x020C) +#define MUX_SEL_DISP4 DISP_REG(0x0210) +#define MUX_ENABLE_DISP0 DISP_REG(0x0300) +#define MUX_ENABLE_DISP1 DISP_REG(0x0304) +#define MUX_ENABLE_DISP2 DISP_REG(0x0308) +#define MUX_ENABLE_DISP3 DISP_REG(0x030c) +#define MUX_ENABLE_DISP4 DISP_REG(0x0310) +#define MUX_STAT_DISP0 DISP_REG(0x0400) +#define MUX_STAT_DISP1 DISP_REG(0x0404) +#define MUX_STAT_DISP2 DISP_REG(0x0408) +#define MUX_STAT_DISP3 DISP_REG(0x040c) +#define MUX_STAT_DISP4 DISP_REG(0x0410) +#define MUX_IGNORE_DISP0 DISP_REG(0x0500) +#define MUX_IGNORE_DISP1 DISP_REG(0x0504) +#define MUX_IGNORE_DISP2 DISP_REG(0x0508) +#define MUX_IGNORE_DISP3 DISP_REG(0x050c) +#define MUX_IGNORE_DISP4 DISP_REG(0x0510) +#define DIV_DISP DISP_REG(0x0600) +#define DIV_STAT_DISP DISP_REG(0x0700) +#define EN_ACLK_DISP DISP_REG(0x0800) +#define EN_PCLK_DISP DISP_REG(0x0900) +#define EN_SCLK_DISP0 DISP_REG(0x0a00) +#define EN_SCLK_DISP1 DISP_REG(0x0a04) +#define EN_IP_DISP DISP_REG(0x0b00) +#define EN_IP_DISP_BUS DISP_REG(0x0b04) + + +/* +*Registers for CMU_EGL +*/ +#define EGL_PLL_LOCK EGL_REG(0x0000) +#define EGL_DPLL_LOCK EGL_REG(0x0004) +#define EGL_PLL_CON0 EGL_REG(0x0100) +#define EGL_PLL_CON1 EGL_REG(0x0104) +#define EGL_PLL_FREQ_DET EGL_REG(0x010c) +#define EGL_DPLL_CON0 EGL_REG(0x0110) +#define EGL_DPLL_CON1 EGL_REG(0x0114) +#define EGL_DPLL_FREQ_DET EGL_REG(0x011c) +#define MUX_SEL_EGL EGL_REG(0x0200) +#define MUX_ENABLE_EGL EGL_REG(0x0300) +#define MUX_STAT_EGL EGL_REG(0x0400) +#define DIV_EGL EGL_REG(0x0600) +#define DIV_EGL_PLL_FDET EGL_REG(0x0604) +#define DIV_STAT_EGL EGL_REG(0x0700) +#define DIV_STAT_EGL_PLL_FDET EGL_REG(0x0704) +#define EN_ACLK_EGL EGL_REG(0x0800) +#define EN_PCLK_EGL EGL_REG(0x0900) +#define EN_SCLK_EGL EGL_REG(0x0a00) +#define EN_IP_EGL EGL_REG(0x0b00) +#define CLKOUT_CMU_EGL EGL_REG(0x0c00) +#define CLKOUT_CMU_EGL_DIV_STAT EGL_REG(0x0c04) +#define ARMCLK_STOPCTRL EGL_REG(0x1000) +#define EAGLE_EMA_CTRL EGL_REG(0x1008) +#define EAGLE_EMA_STATUS EGL_REG(0x100c) +#define PWR_CTRL EGL_REG(0x1020) +#define PWR_CTRL2 EGL_REG(0x1024) +#define CLKSTOP_CTRL EGL_REG(0x1028) +#define INTR_SPREAD_EN EGL_REG(0x1080) +#define INTR_SPREAD_USE_STANDBYWFI EGL_REG(0x1084) +#define INTR_SPREAD_BLOCKING_DURATION EGL_REG(0x1088) +#define CMU_EGL_SPARE0 EGL_REG(0x2000) +#define CMU_EGL_SPARE1 EGL_REG(0x2004) +#define CMU_EGL_SPARE2 EGL_REG(0x2008) +#define CMU_EGL_SPARE3 EGL_REG(0x200c) +#define CMU_EGL_SPARE4 EGL_REG(0x2010) + +/* +*Registers for CMU_FSYS +*/ + +#define MUX_SEL_FSYS0 FSYS_REG(0x0200) +#define MUX_SEL_FSYS1 FSYS_REG(0x0204) +#define MUX_ENABLE_FSYS0 FSYS_REG(0x0300) +#define MUX_ENABLE_FSYS1 FSYS_REG(0x0304) +#define MUX_STAT_FSYS0 FSYS_REG(0x0400) +#define MUX_STAT_FSYS1 FSYS_REG(0x0404) +#define MUX_IGNORE_FSYS0 FSYS_REG(0x0500) +#define MUX_IGNORE_FSYS1 FSYS_REG(0x0504) +#define EN_ACLK_FSYS FSYS_REG(0x0800) +#define EN_ACLK_FSYS_SECURE_RTIC FSYS_REG(0x0804) +#define EN_ACLK_FSYS_SECURE_SMMU_RTIC FSYS_REG(0x0808) +#define EN_PCLK_FSYS FSYS_REG(0x0900) +#define EN_SCLK_FSYS FSYS_REG(0x0a00) +#define EN_IP_FSYS FSYS_REG(0x0b00) +#define EN_IP_FSYS_SECURE_RTIC FSYS_REG(0x0b04) +#define EN_IP_FSYS_SECURE_SMMU_RTIC FSYS_REG(0x0b08) + +/* +*Registers for CMU_G2D +*/ + +#define MUX_SEL_G2D G2D_REG(0x0200) +#define MUX_ENABLE_G2D G2D_REG(0x0300) +#define MUX_STAT_G2D G2D_REG(0x0400) +#define DIV_G2D G2D_REG(0x0600) +#define DIV_STAT_G2D G2D_REG(0x0700) +#define EN_ACLK_G2D G2D_REG(0x0800) +#define EN_ACLK_G2D_SECURE_SSS G2D_REG(0x0804) +#define EN_ACLK_G2D_SECURE_SLIM_SSS G2D_REG(0x0808) +#define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS G2D_REG(0x080c) +#define EN_ACLK_G2D_SECURE_SMMU_SSS G2D_REG(0x0810) +#define EN_ACLK_G2D_SECURE_SMMU_MDMA G2D_REG(0x0814) +#define EN_ACLK_G2D_SECURE_SMMU_G2D G2D_REG(0x0818) +#define EN_PCLK_G2D G2D_REG(0x0900) +#define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS G2D_REG(0x0904) +#define EN_PCLK_G2D_SECURE_SMMU_SSS G2D_REG(0x0908) +#define EN_PCLK_G2D_SECURE_SMMU_MDMA G2D_REG(0x090c) +#define EN_PCLK_G2D_SECURE_SMMU_G2D G2D_REG(0x0910) +#define EN_IP_G2D G2D_REG(0x0b00) +#define EN_IP_G2D_SECURE_SSS G2D_REG(0x0b04) +#define EN_IP_G2D_SECURE_SLIM_SSS G2D_REG(0x0b08) +#define EN_IP_G2D_SECURE_SMMU_SLIM_SSS G2D_REG(0x0b0c) +#define EN_IP_G2D_SECURE_SMMU_SSS G2D_REG(0x0b10) +#define EN_IP_G2D_SECURE_SMMU_MDMA G2D_REG(0x0b14) +#define EN_IP_G2D_SECURE_SMMU_G2D G2D_REG(0x0b18) + +/* +*Registers for CMU_G3D +*/ + +#define G3D_PLL_LOCK G3D_REG(0x0000) +#define G3D_PLL_CON0 G3D_REG(0x0100) +#define G3D_PLL_CON1 G3D_REG(0x0104) +#define G3D_PLL_FDET G3D_REG(0x010c) +#define MUX_SEL_G3D G3D_REG(0x0200) +#define MUX_EN_G3D G3D_REG(0x0300) +#define MUX_STAT_G3D G3D_REG(0x0400) +#define MUX_IGNORE_G3D G3D_REG(0x0500) +#define DIV_G3D G3D_REG(0x0600) +#define DIV_G3D_PLL_FDET G3D_REG(0x0604) +#define DIV_STAT_G3D G3D_REG(0x0700) +#define DIV_STAT_G3D_PLL_FDET G3D_REG(0x0704) +#define EN_ACLK_G3D G3D_REG(0x0800) +#define EN_PCLK_G3D G3D_REG(0x0900) +#define EN_SCLK_G3D G3D_REG(0x0a00) +#define EN_IP_G3D G3D_REG(0x0b00) +#define CLKOUT_CMU_G3D G3D_REG(0x0c00) +#define CLKOUT_CMU_G3D_DIV_STAT G3D_REG(0x0c04) +#define G3DCLK_STOPCTRL G3D_REG(0x1000) +#define G3D_EMA_CTRL G3D_REG(0x1008) +#define G3D_EMA_STATUS G3D_REG(0x100c) + +/* +*Registers for CMU_GSCL +*/ + +#define MUX_SEL_GSCL GSCL_REG(0x0200) +#define MUX_EN_GSCL GSCL_REG(0x0300) +#define MUX_STAT_GSCL GSCL_REG(0x0400) +#define MUX_IGNORE_GSCL GSCL_REG(0x0500) +#define DIV_GSCL GSCL_REG(0x0600) +#define DIV_STAT_GSCL GSCL_REG(0x0700) +#define EN_ACLK_GSCL GSCL_REG(0x0800) +#define EN_ACLK_GSCL_FIMC GSCL_REG(0x0804) +#define EN_ACLK_GSCL_SECURE_SMMU_GSCL0 GSCL_REG(0x0808) +#define EN_ACLK_GSCL_SECURE_SMMU_GSCL1 GSCL_REG(0x080c) +#define EN_ACLK_GSCL_SECURE_SMMU_MSCL0 GSCL_REG(0x0810) +#define EN_ACLK_GSCL_SECURE_SMMU_MSCL1 GSCL_REG(0x0814) +#define EN_PCLK_GSCL GSCL_REG(0x0900) +#define EN_PCLK_GSCL_FIMC GSCL_REG(0x0904) +#define EN_PCLK_GSCL_SECURE_SMMU_GSCL0 GSCL_REG(0x0908) +#define EN_PCLK_GSCL_SECURE_SMMU_GSCL1 GSCL_REG(0x090c) +#define EN_PCLK_GSCL_SECURE_SMMU_MSCL0 GSCL_REG(0x0910) +#define EN_PCLK_GSCL_SECURE_SMMU_MSCL1 GSCL_REG(0x0914) +#define EN_SCLK_GSCL GSCL_REG(0x0a00) +#define EN_SCLK_GSCL_FIMC GSCL_REG(0x0a04) +#define EN_IP_GSCL GSCL_REG(0x0b00) +#define EN_IP_GSCL_FIMC GSCL_REG(0x0b04) +#define EN_IP_GSCL_SECURE_SMMU_GSCL0 GSCL_REG(0x0b08) +#define EN_IP_GSCL_SECURE_SMMU_GSCL1 GSCL_REG(0x0b0c) +#define EN_IP_GSCL_SECURE_SMMU_MSCL0 GSCL_REG(0x0b10) +#define EN_IP_GSCL_SECURE_SMMU_MSCL1 GSCL_REG(0x0b14) + +/* +*Registers for CMU_ISP +*/ +#define MUX_SEL_ISP0 ISP_REG(0x0200) +#define MUX_SEL_ISP1 ISP_REG(0x0204) +#define MUX_ENABLE_ISP0 ISP_REG(0x0300) +#define MUX_ENABLE_ISP1 ISP_REG(0x0304) +#define MUX_STAT_ISP0 ISP_REG(0x0400) +#define MUX_STAT_ISP1 ISP_REG(0x0404) +#define MUX_IGNORE_ISP0 ISP_REG(0x0500) +#define MUX_IGNORE_ISP1 ISP_REG(0x0504) +#define DIV_ISP ISP_REG(0x0600) +#define DIV_STAT_ISP ISP_REG(0x0700) +#define EN_ACLK_ISP0 ISP_REG(0x0800) +#define EN_ACLK_ISP1 ISP_REG(0x0804) +#define EN_PCLK_ISP0 ISP_REG(0x0900) +#define EN_PCLK_ISP1 ISP_REG(0x0904) +#define EN_SCLK_ISP ISP_REG(0x0a00) +#define EN_IP_ISP0 ISP_REG(0x0b00) +#define EN_IP_ISP1 ISP_REG(0x0b04) + +/* +*Registers for CMU_KFC +*/ +#define KFC_PLL_LOCK KFC_REG(0x0000) +#define KFC_PLL_CON0 KFC_REG(0x0100) +#define KFC_PLL_CON1 KFC_REG(0x0104) +#define KFC_PLL_FDET KFC_REG(0x010c) +#define MUX_SEL_KFC0 KFC_REG(0x0200) +#define MUX_SEL_KFC2 KFC_REG(0x0208) +#define MUX_ENABLE_KFC0 KFC_REG(0x0300) +#define MUX_ENABLE_KFC2 KFC_REG(0x0308) +#define MUX_STAT_KFC0 KFC_REG(0x0400) +#define MUX_STAT_KFC2 KFC_REG(0x0408) +#define DIV_KFC KFC_REG(0x0600) +#define DIV_KFC_PLL_FDET KFC_REG(0x0604) +#define DIV_STAT_KFC KFC_REG(0x0700) +#define DIV_STAT_KFC_PLL_FDET KFC_REG(0x0704) +#define EN_ACLK_KFC KFC_REG(0x0800) +#define EN_PCLK_KFC KFC_REG(0x0900) +#define EN_SCLK_KFC KFC_REG(0x0a00) +#define EN_IP_KFC KFC_REG(0x0b00) +#define CLKOUT_CMU_KFC KFC_REG(0x0c00) +#define CLKOUT_CMU_KFC_DIV_STAT KFC_REG(0x0c04) +#define ARMCLK_STOPCTRL_KFC KFC_REG(0x1000) +#define ARM_EMA_CTRL KFC_REG(0x1008) +#define ARM_EMA_STATUS KFC_REG(0x100c) +#define PWR_CTRL_KFC KFC_REG(0x1020) +#define PWR_CTRL2_KFC KFC_REG(0x1024) +#define CLKSTOP_CTRL_KFC KFC_REG(0x1028) +#define INTR_SPREAD_ENABLE_KFC KFC_REG(0x1080) +#define INTR_SPREAD_USE_STANDBYWFI_KFC KFC_REG(0x1084) +#define INTR_SPREAD_BLOCKING_DURATION_KFC KFC_REG(0x1088) +#define CMU_KFC_SPARE0 KFC_REG(0x2000) +#define CMU_KFC_SPARE1 KFC_REG(0x2004) +#define CMU_KFC_SPARE2 KFC_REG(0x2008) +#define CMU_KFC_SPARE3 KFC_REG(0x200c) +#define CMU_KFC_SPARE4 KFC_REG(0x2010) + +/* +*Registers for CMU_MFC +*/ +#define MUX_SEL_MFC MFC_REG(0x0200) +#define MUX_ENABLE_MFC MFC_REG(0x0300) +#define MUX_STAT_MFC MFC_REG(0x0400) +#define DIV_MFC MFC_REG(0x0600) +#define DIV_STAT_MFC MFC_REG(0x0700) +#define EN_ACLK_MFC MFC_REG(0x0800) +#define EN_ACLK_SECURE_SMMU2_MFC MFC_REG(0x0804) +#define EN_PCLK_MFC MFC_REG(0x0900) +#define EN_PCLK_SECURE_SMMU2_MFC MFC_REG(0x0904) +#define EN_IP_MFC MFC_REG(0x0b00) +#define EN_IP_MFC_SECURE_SMMU2_MFC MFC_REG(0x0b04) + +/* +*Registers for CMU_MIF +*/ +#define MEM_PLL_LOCK MIF_REG(0x0000) +#define BUS_PLL_LOCK MIF_REG(0x0004) +#define MEDIA_PLL_LOCK MIF_REG(0x0008) +#define MEM_PLL_CON0 MIF_REG(0x0100) +#define MEM_PLL_CON1 MIF_REG(0x0104) +#define MEM_PLL_FDET MIF_REG(0x010c) +#define BUS_PLL_CON0 MIF_REG(0x0110) +#define BUS_PLL_CON1 MIF_REG(0x0114) +#define BUS_PLL_FDET MIF_REG(0x011c) +#define MEDIA_PLL_CON0 MIF_REG(0x0120) +#define MEDIA_PLL_CON1 MIF_REG(0x0124) +#define MEDIA_PLL_FDET MIF_REG(0x012c) +#define MUX_SEL_MIF MIF_REG(0x0200) +#define MUX_ENABLE_MIF MIF_REG(0x0300) +#define MUX_STAT_MIF MIF_REG(0x0400) +#define MUX_IGNORE_MIF MIF_REG(0x0500) +#define DIV_MIF MIF_REG(0x0600) +#define DIV_MIF_PLL_FDET MIF_REG(0x0604) +#define DIV_STAT_MIF MIF_REG(0x0700) +#define DIV_STAT_MIF_PLL_FDET MIF_REG(0x0704) +#define EN_ACLK_MIF MIF_REG(0x0800) +#define EN_ACLK_MIF_SECURE_DREX1_TZ MIF_REG(0x0804) +#define EN_ACLK_MIF_SECURE_DREX0_TZ MIF_REG(0x0808) +#define EN_ACLK_MIF_SECURE_INTMEM MIF_REG(0x080c) +#define EN_PCLK_MIF MIF_REG(0x0900) +#define EN_PCLK_MIF_SECURE_MONOCNT MIF_REG(0x0904) +#define EN_PCLK_MIF_SECURE_RTC_APBIF MIF_REG(0x0908) +#define EN_PCLK_MIF_SECURE_DREX1_TZ MIF_REG(0x090c) +#define EN_PCLK_MIF_SECURE_DREX0_TZ MIF_REG(0x0910) +#define EN_SCLK_MIF MIF_REG(0x0a00) +#define EN_IP_MIF MIF_REG(0x0b00) +#define EN_IP_MIF_SECURE_MONOCNT MIF_REG(0x0b04) +#define EN_IP_MIF_SECURE_RTC_APBIF MIF_REG(0x0b08) +#define EN_IP_MIF_SECURE_DREX1_TZ MIF_REG(0x0b0c) +#define EN_IP_MIF_SECURE_DREX0_TZ MIF_REG(0x0b10) +#define EN_IP_MIF_SECURE_INTEMEM MIF_REG(0x0b14) +#define CLKOUT_CMU_MIF_DIV_STAT MIF_REG(0x0c04) +#define DREX_FREQ_CTRL MIF_REG(0x1000) +#define PAUSE MIF_REG(0x1004) +#define DDRPHY_LOCK_CTRL MIF_REG(0x1008) +#define CLKOUT_CMU_MIF MIF_REG(0xcb00) + +/* +*Registers for CMU_PERI +*/ +#define MUX_SEL_PERI PERI_REG(0x0200) +#define MUX_SEL_PERI1 PERI_REG(0x0204) +#define MUX_ENABLE_PERI PERI_REG(0x0300) +#define MUX_ENABLE_PERI1 PERI_REG(0x0304) +#define MUX_STAT_PERI PERI_REG(0x0400) +#define MUX_STAT_PERI1 PERI_REG(0x0404) +#define MUX_IGNORE_PERI PERI_REG(0x0500) +#define MUX_IGNORE_PERI1 PERI_REG(0x0504) +#define DIV_PERI PERI_REG(0x0600) +#define DIV_STAT_PERI PERI_REG(0x0700) +#define EN_PCLK_PERI0 PERI_REG(0x0800) +#define EN_PCLK_PERI1 PERI_REG(0x0804) +#define EN_PCLK_PERI2 PERI_REG(0x0808) +#define EN_PCLK_PERI3 PERI_REG(0x080c) +#define EN_PCLK_PERI_SECURE_CHIPID PERI_REG(0x0810) +#define EN_PCLK_PERI_SECURE_PROVKEY0 PERI_REG(0x0814) +#define EN_PCLK_PERI_SECURE_PROVKEY1 PERI_REG(0x0818) +#define EN_PCLK_PERI_SECURE_SECKEY PERI_REG(0x081c) +#define EN_PCLK_PERI_SECURE_ANTIRBKCNT PERI_REG(0x0820) +#define EN_PCLK_PERI_SECURE_TOP_RTC PERI_REG(0x0824) +#define EN_PCLK_PERI_SECURE_TZPC PERI_REG(0x0828) +#define EN_SCLK_PERI PERI_REG(0x0a00) +#define EN_SCLK_PERI_SECURE_TOP_RTC PERI_REG(0x0a04) +#define EN_IP_PERI0 PERI_REG(0x0b00) +#define EN_IP_PERI1 PERI_REG(0x0b04) +#define EN_IP_PERI2 PERI_REG(0x0b08) +#define EN_IP_PERI_SECURE_CHIPID PERI_REG(0x0b0c) +#define EN_IP_PERI_SECURE_PROVKEY0 PERI_REG(0x0b10) +#define EN_IP_PERI_SECURE_PROVKEY1 PERI_REG(0x0b14) +#define EN_IP_PERI_SECURE_SECKEY PERI_REG(0x0b18) +#define EN_IP_PERI_SECURE_ANTIRBKCNT PERI_REG(0x0b1c) +#define EN_IP_PERI_SECURE_TOP_RTC PERI_REG(0x0b20) +#define EN_IP_PERI_SECURE_TZPC PERI_REG(0x0b24) + +/* +*Registers for CMU_TOP +*/ +#define DISP_PLL_LOCK TOP_REG(0x0000) +#define AUD_PLL_LOCK TOP_REG(0x0004) +#define DISP_PLL_CON0 TOP_REG(0x0100) +#define DISP_PLL_CON1 TOP_REG(0x0104) +#define DISP_PLL_FDET TOP_REG(0x0108) +#define AUD_PLL_CON0 TOP_REG(0x0110) +#define AUD_PLL_CON1 TOP_REG(0x0114) +#define AUD_PLL_CON2 TOP_REG(0x0118) +#define AUD_PLL_FDET TOP_REG(0x011c) +#define MUX_SEL_TOP_PLL0 TOP_REG(0x0200) +#define MUX_SEL_TOP_MFC TOP_REG(0x0204) +#define MUX_SEL_TOP_G2D TOP_REG(0x0208) +#define MUX_SEL_TOP_GSCL TOP_REG(0x020c) +#define MUX_SEL_TOP_ISP10 TOP_REG(0x0214) +#define MUX_SEL_TOP_ISP11 TOP_REG(0x0218) +#define MUX_SEL_TOP_DISP0 TOP_REG(0x021c) +#define MUX_SEL_TOP_DISP1 TOP_REG(0x0220) +#define MUX_SEL_TOP_BUS TOP_REG(0x0224) +#define MUX_SEL_TOP_PERI0 TOP_REG(0x0228) +#define MUX_SEL_TOP_PERI1 TOP_REG(0x022c) +#define MUX_SEL_TOP_FSYS TOP_REG(0x0230) +#define MUX_ENABLE_TOP_PLL0 TOP_REG(0x0300) +#define MUX_ENABLE_TOP_MFC TOP_REG(0x0304) +#define MUX_ENABLE_TOP_G2D TOP_REG(0x0308) +#define MUX_ENABLE_TOP_GSCL TOP_REG(0x030c) +#define MUX_ENABLE_TOP_ISP10 TOP_REG(0x0314) +#define MUX_ENABLE_TOP_ISP11 TOP_REG(0x0318) +#define MUX_ENABLE_TOP_DISP0 TOP_REG(0x031c) +#define MUX_ENABLE_TOP_DISP1 TOP_REG(0x0320) +#define MUX_ENABLE_TOP_BUS TOP_REG(0x0324) +#define MUX_ENABLE_TOP_PERI0 TOP_REG(0x0328) +#define MUX_ENABLE_TOP_PERI1 TOP_REG(0x032c) +#define MUX_ENABLE_TOP_FSYS TOP_REG(0x0330) +#define MUX_STAT_TOP_PLL0 TOP_REG(0x0400) +#define MUX_STAT_TOP_MFC TOP_REG(0x0404) +#define MUX_STAT_TOP_G2D TOP_REG(0x0408) +#define MUX_STAT_TOP_GSCL TOP_REG(0x040c) +#define MUX_STAT_TOP_ISP10 TOP_REG(0x0414) +#define MUX_STAT_TOP_ISP11 TOP_REG(0x0418) +#define MUX_STAT_TOP_DISP0 TOP_REG(0x041c) +#define MUX_STAT_TOP_DISP1 TOP_REG(0x0420) +#define MUX_STAT_TOP_BUS TOP_REG(0x0424) +#define MUX_STAT_TOP_PERI0 TOP_REG(0x0428) +#define MUX_STAT_TOP_PERI1 TOP_REG(0x042c) +#define MUX_STAT_TOP_FSYS TOP_REG(0x0430) +#define MUX_IGNORE_TOP_PLL0 TOP_REG(0x0500) +#define MUX_IGNORE_TOP_MFC TOP_REG(0x0504) +#define MUX_IGNORE_TOP_G2D TOP_REG(0x0508) +#define MUX_IGNORE_TOP_GSCL TOP_REG(0x050c) +#define MUX_IGNORE_TOP_ISP10 TOP_REG(0x0514) +#define MUX_IGNORE_TOP_ISP11 TOP_REG(0x0518) +#define MUX_IGNORE_TOP_DISP0 TOP_REG(0x051c) +#define MUX_IGNORE_TOP_DISP1 TOP_REG(0x0520) +#define MUX_IGNORE_TOP_BUS TOP_REG(0x0524) +#define MUX_IGNORE_TOP_PERI0 TOP_REG(0x0528) +#define MUX_IGNORE_TOP_PERI1 TOP_REG(0x052c) +#define MUX_IGNORE_TOP_FSYS TOP_REG(0x0530) +#define DIV_TOP_G2D_MFC TOP_REG(0x0600) +#define DIV_TOP_GSCL_ISP0 TOP_REG(0x0604) +#define DIV_TOP_ISP10 TOP_REG(0x0608) +#define DIV_TOP_ISP11 TOP_REG(0x060c) +#define DIV_TOP_DISP TOP_REG(0x0610) +#define DIV_TOP_BUS TOP_REG(0x0614) +#define DIV_TOP_PERI0 TOP_REG(0x0618) +#define DIV_TOP_PERI1 TOP_REG(0x061c) +#define DIV_TOP_PERI2 TOP_REG(0x0620) +#define DIV_TOP_FSYS0 TOP_REG(0x0624) +#define DIV_TOP_FSYS1 TOP_REG(0x0628) +#define DIV_TOP_HPM TOP_REG(0x062c) +#define DIV_TOP_PLL_FDET TOP_REG(0x0630) +#define DIV_STAT_TOP_G2D_MFC TOP_REG(0x0700) +#define DIV_STAT_TOP_GSCL_ISP0 TOP_REG(0x0704) +#define DIV_STAT_TOP_ISP10 TOP_REG(0x0708) +#define DIV_STAT_TOP_ISP11 TOP_REG(0x070c) +#define DIV_STAT_TOP_DISP TOP_REG(0x0710) +#define DIV_STAT_TOP_BUS TOP_REG(0x0714) +#define DIV_STAT_TOP_PERI0 TOP_REG(0x0718) +#define DIV_STAT_TOP_PERI1 TOP_REG(0x071c) +#define DIV_STAT_TOP_PERI2 TOP_REG(0x0720) +#define DIV_STAT_TOP_FSYS0 TOP_REG(0x0724) +#define DIV_STAT_TOP_FSYS1 TOP_REG(0x0728) +#define DIV_STAT_TOP_HPM TOP_REG(0x072c) +#define DIV_STAT_TOP_PLL_FDET TOP_REG(0x0730) +#define EN_ACLK_TOP TOP_REG(0x0800) +#define EN_SCLK_TOP TOP_REG(0x0a00) +#define EN_IP_TOP TOP_REG(0x0b00) +#define CLKOUT_CMU_TOP TOP_REG(0x0c00) +#define CLKOUT_CMU_TOP_DIV_STAT TOP_REG(0x0c04) + +#endif /*__CLK_EXYNOS5260_H */ +