From patchwork Mon Feb 24 13:22:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 3709291 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9F37A9F2F7 for ; Mon, 24 Feb 2014 13:23:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 65EF82015D for ; Mon, 24 Feb 2014 13:23:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D9DD620160 for ; Mon, 24 Feb 2014 13:23:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752657AbaBXNXb (ORCPT ); Mon, 24 Feb 2014 08:23:31 -0500 Received: from mailout1.w1.samsung.com ([210.118.77.11]:19073 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752643AbaBXNXa (ORCPT ); Mon, 24 Feb 2014 08:23:30 -0500 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N1I008C3575P280@mailout1.w1.samsung.com>; Mon, 24 Feb 2014 13:23:29 +0000 (GMT) X-AuditID: cbfec7f5-b7fc96d000004885-21-530b47d02ad5 Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 76.8E.18565.0D74B035; Mon, 24 Feb 2014 13:23:28 +0000 (GMT) Received: from AMDC1061.digital.local ([106.116.147.88]) by eusync4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N1I00GYJ56PQ070@eusync4.samsung.com>; Mon, 24 Feb 2014 13:23:27 +0000 (GMT) From: Andrzej Hajda To: linux-arm-kernel@lists.infradead.org Cc: Andrzej Hajda , Tomasz Figa , Kukjin Kim , Mike Turquette , Kyungmin Park , devicetree@vger.kernel.org (moderated list:OPEN FIRMWARE AND...), linux-samsung-soc@vger.kernel.org (moderated list:ARM/S5P EXYNOS AR...) Subject: [PATCH RESEND v2 3/4] ARM: dts: exynos5420: convert magic numbers to macros in clock bindings Date: Mon, 24 Feb 2014 14:22:59 +0100 Message-id: <1393248180-17408-4-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 1.8.3.2 In-reply-to: <1393248180-17408-1-git-send-email-a.hajda@samsung.com> References: <1393248180-17408-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGJMWRmVeSWpSXmKPExsVy+t/xa7oX3LmDDZoOMlrcWneO1WL+ESDR u+Aqm8XZpjfsFpseX2O1mHF+H5PF0wkX2SzWz3jN4sDhcefaHjaPzUvqPfq2rGL0+LxJLoAl issmJTUnsyy1SN8ugSvjyq7fjAUrGxkr7hzsYGtgvJPQxcjJISFgInF2zl92CFtM4sK99Wxd jFwcQgJLGSW2Xm9lgnD6mCROT7jMClLFJqAp8XfzTTYQW0RAQ2JK12N2kCJmgctMEkue/QBL CAtkSFz9sZ4FxGYRUJXYvfYomM0r4Cyxv+ci1DoFiWVf1jJ3MXJwcAq4SLQcKwEJCwGVHF94 jnECI+8CRoZVjKKppckFxUnpuUZ6xYm5xaV56XrJ+bmbGCFh9XUH49JjVocYBTgYlXh4Jaq5 goVYE8uKK3MPMUpwMCuJ8EY5cAcL8aYkVlalFuXHF5XmpBYfYmTi4JRqYBT5oiI389p2xbal Md6rdSN2lynGTuf9oNYWfTn18KKF5kWbCnIXlceluyxtvaxveL32VsHZ2MMM7woq++fopG7x WbTyX2+dW3rdp6U9X6+9fynMY9Z0P75t5R3eGZkNWdZTSq47rn5UZx0U26rya+rNziPOgc9P s0z3jvIq4jY5z38sO3r/FCWW4oxEQy3mouJEAKZinoEJAgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch replaces magic numbers with macros defined in DT header in exynos5420 clock bindings. Signed-off-by: Andrzej Hajda Signed-off-by: Kyungmin Park Acked-by: Tomasz Figa Acked-by: Mike Turquette --- .../devicetree/bindings/clock/exynos5420-clock.txt | 184 +-------------------- arch/arm/boot/dts/exynos5420.dtsi | 95 +++++------ 2 files changed, 55 insertions(+), 224 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 458f347..ca88c97 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -13,184 +13,12 @@ Required Properties: - #clock-cells: should be 1. -The following is the list of clocks generated by the controller. Each clock is -assigned an identifier and client nodes use this identifier to specify the -clock which they consume. +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. - - [Core Clocks] - - Clock ID - ---------------------------- - - fin_pll 1 - - [Clock Gate for Special Clocks] - - Clock ID - ---------------------------- - sclk_uart0 128 - sclk_uart1 129 - sclk_uart2 130 - sclk_uart3 131 - sclk_mmc0 132 - sclk_mmc1 133 - sclk_mmc2 134 - sclk_spi0 135 - sclk_spi1 136 - sclk_spi2 137 - sclk_i2s1 138 - sclk_i2s2 139 - sclk_pcm1 140 - sclk_pcm2 141 - sclk_spdif 142 - sclk_hdmi 143 - sclk_pixel 144 - sclk_dp1 145 - sclk_mipi1 146 - sclk_fimd1 147 - sclk_maudio0 148 - sclk_maupcm0 149 - sclk_usbd300 150 - sclk_usbd301 151 - sclk_usbphy300 152 - sclk_usbphy301 153 - sclk_unipro 154 - sclk_pwm 155 - sclk_gscl_wa 156 - sclk_gscl_wb 157 - sclk_hdmiphy 158 - - [Peripheral Clock Gates] - - Clock ID - ---------------------------- - - aclk66_peric 256 - uart0 257 - uart1 258 - uart2 259 - uart3 260 - i2c0 261 - i2c1 262 - i2c2 263 - i2c3 264 - i2c4 265 - i2c5 266 - i2c6 267 - i2c7 268 - i2c_hdmi 269 - tsadc 270 - spi0 271 - spi1 272 - spi2 273 - keyif 274 - i2s1 275 - i2s2 276 - pcm1 277 - pcm2 278 - pwm 279 - spdif 280 - i2c8 281 - i2c9 282 - i2c10 283 - aclk66_psgen 300 - chipid 301 - sysreg 302 - tzpc0 303 - tzpc1 304 - tzpc2 305 - tzpc3 306 - tzpc4 307 - tzpc5 308 - tzpc6 309 - tzpc7 310 - tzpc8 311 - tzpc9 312 - hdmi_cec 313 - seckey 314 - mct 315 - wdt 316 - rtc 317 - tmu 318 - tmu_gpu 319 - pclk66_gpio 330 - aclk200_fsys2 350 - mmc0 351 - mmc1 352 - mmc2 353 - sromc 354 - ufs 355 - aclk200_fsys 360 - tsi 361 - pdma0 362 - pdma1 363 - rtic 364 - usbh20 365 - usbd300 366 - usbd301 377 - aclk400_mscl 380 - mscl0 381 - mscl1 382 - mscl2 383 - smmu_mscl0 384 - smmu_mscl1 385 - smmu_mscl2 386 - aclk333 400 - mfc 401 - smmu_mfcl 402 - smmu_mfcr 403 - aclk200_disp1 410 - dsim1 411 - dp1 412 - hdmi 413 - aclk300_disp1 420 - fimd1 421 - smmu_fimd1 422 - aclk166 430 - mixer 431 - aclk266 440 - rotator 441 - mdma1 442 - smmu_rotator 443 - smmu_mdma1 444 - aclk300_jpeg 450 - jpeg 451 - jpeg2 452 - smmu_jpeg 453 - aclk300_gscl 460 - smmu_gscl0 461 - smmu_gscl1 462 - gscl_wa 463 - gscl_wb 464 - gscl0 465 - gscl1 466 - clk_3aa 467 - aclk266_g2d 470 - sss 471 - slim_sss 472 - mdma0 473 - aclk333_g2d 480 - g2d 481 - aclk333_432_gscl 490 - smmu_3aa 491 - smmu_fimcl0 492 - smmu_fimcl1 493 - smmu_fimcl3 494 - fimc_lite3 495 - aclk_g3d 500 - g3d 501 - smmu_mixer 502 - - Mux ID - ---------------------------- - - mout_hdmi 640 - - Divider ID - ---------------------------- - - dout_pixel 768 +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos5420.h header and can be used in device +tree sources. Example 1: An example of a clock controller node is listed below. @@ -208,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock compatible = "samsung,exynos4210-uart"; reg = <0x13820000 0x100>; interrupts = <0 54 0>; - clocks = <&clock 259>, <&clock 130>; + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 45e2e65..e3329af 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -13,6 +13,7 @@ * published by the Free Software Foundation. */ +#include #include "exynos5.dtsi" #include "exynos5420-pinctrl.dtsi" @@ -119,7 +120,8 @@ compatible = "samsung,exynos5420-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; - clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, + <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; @@ -127,7 +129,7 @@ compatible = "samsung,mfc-v7"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; - clocks = <&clock 401>; + clocks = <&clock CLK_MFC>; clock-names = "mfc"; }; @@ -137,7 +139,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x12200000 0x2000>; - clocks = <&clock 351>, <&clock 132>; + clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; status = "disabled"; @@ -149,7 +151,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x12210000 0x2000>; - clocks = <&clock 352>, <&clock 133>; + clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; status = "disabled"; @@ -161,7 +163,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x12220000 0x1000>; - clocks = <&clock 353>, <&clock 134>; + clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; status = "disabled"; @@ -175,7 +177,7 @@ interrupt-parent = <&mct_map>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>; - clocks = <&clock 1>, <&clock 315>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; mct_map: mct-map { @@ -269,7 +271,7 @@ }; rtc@101E0000 { - clocks = <&clock 317>; + clocks = <&clock CLK_RTC>; clock-names = "rtc"; status = "disabled"; }; @@ -296,7 +298,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; interrupts = <0 34 0>; - clocks = <&clock 362>; + clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -307,7 +309,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; interrupts = <0 35 0>; - clocks = <&clock 363>; + clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -318,7 +320,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; interrupts = <0 33 0>; - clocks = <&clock 473>; + clocks = <&clock CLK_MDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -329,7 +331,7 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; interrupts = <0 124 0>; - clocks = <&clock 442>; + clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; #dma-channels = <8>; @@ -360,7 +362,7 @@ dmas = <&pdma1 12 &pdma1 11>; dma-names = "tx", "rx"; - clocks = <&clock 275>, <&clock 138>; + clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; clock-names = "iis", "i2s_opclk0"; pinctrl-names = "default"; pinctrl-0 = <&i2s1_bus>; @@ -373,7 +375,7 @@ dmas = <&pdma0 12 &pdma0 11>; dma-names = "tx", "rx"; - clocks = <&clock 276>, <&clock 139>; + clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; clock-names = "iis", "i2s_opclk0"; pinctrl-names = "default"; pinctrl-0 = <&i2s2_bus>; @@ -391,7 +393,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; - clocks = <&clock 271>, <&clock 135>; + clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; clock-names = "spi", "spi_busclk0"; status = "disabled"; }; @@ -407,7 +409,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; - clocks = <&clock 272>, <&clock 136>; + clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; clock-names = "spi", "spi_busclk0"; status = "disabled"; }; @@ -423,28 +425,28 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; - clocks = <&clock 273>, <&clock 137>; + clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; clock-names = "spi", "spi_busclk0"; status = "disabled"; }; serial@12C00000 { - clocks = <&clock 257>, <&clock 128>; + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C10000 { - clocks = <&clock 258>, <&clock 129>; + clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C20000 { - clocks = <&clock 259>, <&clock 130>; + clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; }; serial@12C30000 { - clocks = <&clock 260>, <&clock 131>; + clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; }; @@ -453,7 +455,7 @@ reg = <0x12dd0000 0x100>; samsung,pwm-outputs = <0>, <1>, <2>, <3>; #pwm-cells = <3>; - clocks = <&clock 279>; + clocks = <&clock CLK_PWM>; clock-names = "timers"; }; @@ -464,7 +466,7 @@ }; dp-controller@145B0000 { - clocks = <&clock 412>; + clocks = <&clock CLK_DP1>; clock-names = "dp"; phys = <&dp_phy>; phy-names = "dp"; @@ -472,7 +474,7 @@ fimd@14400000 { samsung,power-domain = <&disp_pd>; - clocks = <&clock 147>, <&clock 421>; + clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; }; @@ -480,7 +482,7 @@ compatible = "samsung,exynos-adc-v2"; reg = <0x12D10000 0x100>, <0x10040720 0x4>; interrupts = <0 106 0>; - clocks = <&clock 270>; + clocks = <&clock CLK_TSADC>; clock-names = "adc"; #io-channel-cells = <1>; io-channel-ranges; @@ -493,7 +495,7 @@ interrupts = <0 56 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 261>; + clocks = <&clock CLK_I2C0>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_bus>; @@ -506,7 +508,7 @@ interrupts = <0 57 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 262>; + clocks = <&clock CLK_I2C1>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_bus>; @@ -519,7 +521,7 @@ interrupts = <0 58 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 263>; + clocks = <&clock CLK_I2C2>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c2_bus>; @@ -532,7 +534,7 @@ interrupts = <0 59 0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&clock 264>; + clocks = <&clock CLK_I2C3>; clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c3_bus>; @@ -547,7 +549,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_hs_bus>; - clocks = <&clock 265>; + clocks = <&clock CLK_I2C4>; clock-names = "hsi2c"; status = "disabled"; }; @@ -560,7 +562,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_hs_bus>; - clocks = <&clock 266>; + clocks = <&clock CLK_I2C5>; clock-names = "hsi2c"; status = "disabled"; }; @@ -573,7 +575,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c6_hs_bus>; - clocks = <&clock 267>; + clocks = <&clock CLK_I2C6>; clock-names = "hsi2c"; status = "disabled"; }; @@ -586,7 +588,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_hs_bus>; - clocks = <&clock 268>; + clocks = <&clock CLK_I2C7>; clock-names = "hsi2c"; status = "disabled"; }; @@ -599,7 +601,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c8_hs_bus>; - clocks = <&clock 281>; + clocks = <&clock CLK_I2C8>; clock-names = "hsi2c"; status = "disabled"; }; @@ -612,7 +614,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c9_hs_bus>; - clocks = <&clock 282>; + clocks = <&clock CLK_I2C9>; clock-names = "hsi2c"; status = "disabled"; }; @@ -625,7 +627,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2c10_hs_bus>; - clocks = <&clock 283>; + clocks = <&clock CLK_I2C10>; clock-names = "hsi2c"; status = "disabled"; }; @@ -634,8 +636,9 @@ compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; interrupts = <0 95 0>; - clocks = <&clock 413>, <&clock 143>, <&clock 768>, - <&clock 158>, <&clock 640>; + clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, + <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, + <&clock CLK_MOUT_HDMI>; clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"; status = "disabled"; @@ -645,7 +648,7 @@ compatible = "samsung,exynos5420-mixer"; reg = <0x14450000 0x10000>; interrupts = <0 94 0>; - clocks = <&clock 431>, <&clock 143>; + clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; clock-names = "mixer", "sclk_hdmi"; }; @@ -653,7 +656,7 @@ compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; - clocks = <&clock 465>; + clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; samsung,power-domain = <&gsc_pd>; }; @@ -662,7 +665,7 @@ compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <0 86 0>; - clocks = <&clock 466>; + clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; samsung,power-domain = <&gsc_pd>; }; @@ -676,7 +679,7 @@ compatible = "samsung,exynos5420-tmu"; reg = <0x10060000 0x100>; interrupts = <0 65 0>; - clocks = <&clock 318>; + clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; }; @@ -684,7 +687,7 @@ compatible = "samsung,exynos5420-tmu"; reg = <0x10064000 0x100>; interrupts = <0 183 0>; - clocks = <&clock 318>; + clocks = <&clock CLK_TMU>; clock-names = "tmu_apbif"; }; @@ -692,7 +695,7 @@ compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x10068000 0x100>, <0x1006c000 0x4>; interrupts = <0 184 0>; - clocks = <&clock 318>, <&clock 318>; + clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; }; @@ -700,7 +703,7 @@ compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x1006c000 0x100>, <0x100a0000 0x4>; interrupts = <0 185 0>; - clocks = <&clock 318>, <&clock 319>; + clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; }; @@ -708,7 +711,7 @@ compatible = "samsung,exynos5420-tmu-ext-triminfo"; reg = <0x100a0000 0x100>, <0x10068000 0x4>; interrupts = <0 215 0>; - clocks = <&clock 319>, <&clock 318>; + clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; }; @@ -716,7 +719,7 @@ compatible = "samsung,exynos5420-wdt"; reg = <0x101D0000 0x100>; interrupts = <0 42 0>; - clocks = <&clock 316>; + clocks = <&clock CLK_WDT>; clock-names = "watchdog"; samsung,syscon-phandle = <&pmu_system_controller>; };