From patchwork Tue Mar 4 11:12:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 3761191 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 13E65BF40C for ; Tue, 4 Mar 2014 11:13:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 25B3F2042C for ; Tue, 4 Mar 2014 11:13:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0B142203EC for ; Tue, 4 Mar 2014 11:13:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756992AbaCDLN0 (ORCPT ); Tue, 4 Mar 2014 06:13:26 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:40922 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756709AbaCDLNY (ORCPT ); Tue, 4 Mar 2014 06:13:24 -0500 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N1W00C33SIB9GD0@mailout1.samsung.com>; Tue, 04 Mar 2014 20:13:23 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.126]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 03.34.10364.355B5135; Tue, 04 Mar 2014 20:13:23 +0900 (KST) X-AuditID: cbfee690-b7f266d00000287c-a5-5315b5531538 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 59.33.29263.355B5135; Tue, 04 Mar 2014 20:13:23 +0900 (KST) Received: from localhost.localdomain ([107.108.83.245]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N1W00CR9SHWKK90@mmp2.samsung.com>; Tue, 04 Mar 2014 20:13:23 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, r.sh.open@gmail.com, Pankaj Dubey , Rahul Sharma Subject: [PATCH v4 2/5] clk/samsung: add support for pll2550xx Date: Tue, 04 Mar 2014 16:42:35 +0530 Message-id: <1393931558-23502-3-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1393931558-23502-1-git-send-email-rahul.sharma@samsung.com> References: <1393931558-23502-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpikeLIzCtJLcpLzFFi42JZI2JSpxu8VTTYYMkNGYv5R86xWnzf9YXd onfBVTaLTY+vsVrMOL+PyeLphItsFou2AiUWvoi3mLLoMKvFql1/GB24PHbOusvucefaHjaP zUvqPfq2rGL0+LxJLoA1issmJTUnsyy1SN8ugSvj/qlPbAWTVCteL1zN3sD4TK6LkZNDQsBE 4vGJz+wQtpjEhXvr2boYuTiEBJYySkyfe4QRpqj35Bl2iMR0Roln64+wgCSEBNqZJDZPTgex 2QR0JWYffAbUwMEhIpApsXFLLkg9s8BxRonf7z+xgdQIC9hJTFv1gBXEZhFQlfjS+RxsM6+A h0T3vy8sIL0SAgoScybZgIQ5BTwlpu45wQSxykPi1IY2RpCZEgK72CU6DvYwQcwRkPg2+RBU r6zEpgPMEDdLShxccYNlAqPwAkaGVYyiqQXJBcVJ6UUmesWJucWleel6yfm5mxiB4X/637MJ OxjvHbA+xJgMNG4is5Rocj4wfvJK4g2NzYwsTE1MjY3MLc1IE1YS51V7lBQkJJCeWJKanZpa kFoUX1Sak1p8iJGJg1OqgXGGxZkp0a4nL8j6TdrGKzzNrHhjulUT6wJXuTIzm9YZkmxhXv9K TkolH2q3MZvENftxm8mbNQcuRn3hfz53xrLOZVfawj8oJyb63m9NXPTeMHyHX1fjSk0ba07b JW0X7HvmaUTM29BxUGnfwfL6RwdPKk6+5pV96p3EjKSZj2+IHLW+dWZ/XbMSS3FGoqEWc1Fx IgBomR5VlQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPIsWRmVeSWpSXmKPExsVy+t9jQd3graLBBnvnCFvMP3KO1eL7ri/s Fr0LrrJZbHp8jdVixvl9TBZPJ1xks1i0FSix8EW8xZRFh1ktVu36w+jA5bFz1l12jzvX9rB5 bF5S79G3ZRWjx+dNcgGsUQ2MNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJ uam2Si4+AbpumTlARykplCXmlAKFAhKLi5X07TBNCA1x07WAaYzQ9Q0JgusxMkADCWsYM+6f +sRWMEm14vXC1ewNjM/kuhg5OSQETCR6T55hh7DFJC7cW8/WxcjFISQwnVHi2fojLCAJIYF2 JonNk9NBbDYBXYnZB58xdjFycIgIZEps3JILUs8scJxR4vf7T2wgNcICdhLTVj1gBbFZBFQl vnQ+B1vAK+Ah0f3vCwtIr4SAgsScSTYgYU4BT4mpe04wQazykDi1oY1xAiPvAkaGVYyiqQXJ BcVJ6bmGesWJucWleel6yfm5mxjB0fVMagfjygaLQ4wCHIxKPLwzpokEC7EmlhVX5h5ilOBg VhLhVVwoGizEm5JYWZValB9fVJqTWnyIMRnoqInMUqLJ+cDIzyuJNzQ2MTc1NrU0sTAxsyRN WEmc90CrdaCQQHpiSWp2ampBahHMFiYOTqkGxlnzZx34v+x4kWBm8LGHDvpCp74ePpG5Pe3v 3N/CC6WEdkxinxSTt2p/bq7uykAm0/nbfu1nTRKKdnE/9jLDXST7l2CKqC5T/cyfCdKL/KZ2 H+macLXF8KtbpEvhxCbJTdK/XxmZzjt39mju3Kc55bO4j1abmrkeuCj1VOb9Ug2bhcLvCsIO rVViKc5INNRiLipOBABZRu4y8gIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Pankaj Dubey exynos5260 use pll2550xx and it has different bit fields for P,M,S values as compared to pll2550. Support for pll2550xx is added here. Signed-off-by: Pankaj Dubey Signed-off-by: Rahul Sharma Signed-off-by: Arun Kumar K Acked-by: Tomasz Figa --- drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 108 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 1f310be..3eb2788 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -947,6 +947,108 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, return clk; } +/* + * PLL2550xx Clock Type + */ + +/* Maximum lock time can be 270 * PDIV cycles */ +#define PLL2550XX_LOCK_FACTOR 270 + +#define PLL2550XX_M_MASK 0x3FF +#define PLL2550XX_P_MASK 0x3F +#define PLL2550XX_S_MASK 0x7 +#define PLL2550XX_LOCK_STAT_MASK 0x1 +#define PLL2550XX_M_SHIFT 9 +#define PLL2550XX_P_SHIFT 3 +#define PLL2550XX_S_SHIFT 0 +#define PLL2550XX_LOCK_STAT_SHIFT 21 + +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, pll_con; + u64 fvco = parent_rate; + + pll_con = __raw_readl(pll->con_reg); + mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; + pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; + sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) +{ + u32 old_mdiv, old_pdiv; + + old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; + old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; + + return mdiv != old_mdiv || pdiv != old_pdiv; +} + +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 tmp; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + tmp = __raw_readl(pll->con_reg); + + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { + /* If only s change, change just s value only*/ + tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT); + tmp |= rate->sdiv << PLL2550XX_S_SHIFT; + __raw_writel(tmp, pll->con_reg); + + return 0; + } + + /* Set PLL lock time. */ + __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); + + /* Change PLL PMS values */ + tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) | + (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) | + (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT)); + tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | + (rate->pdiv << PLL2550XX_P_SHIFT) | + (rate->sdiv << PLL2550XX_S_SHIFT); + __raw_writel(tmp, pll->con_reg); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK + << PLL2550XX_LOCK_STAT_SHIFT))); + + return 0; +} + +static const struct clk_ops samsung_pll2550xx_clk_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll2550xx_set_rate, +}; + +static const struct clk_ops samsung_pll2550xx_clk_min_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, struct samsung_pll_clock *pll_clk, void __iomem *base) @@ -1048,6 +1150,11 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, init.ops = &samsung_s3c2440_mpll_clk_min_ops; else init.ops = &samsung_s3c2440_mpll_clk_ops; + case pll_2550xx: + if (!pll->rate_table) + init.ops = &samsung_pll2550xx_clk_min_ops; + else + init.ops = &samsung_pll2550xx_clk_ops; break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 6428bcc..ec4bc1d 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -31,6 +31,7 @@ enum samsung_pll_type { pll_s3c2410_mpll, pll_s3c2410_upll, pll_s3c2440_mpll, + pll_2550xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \