From patchwork Wed Mar 12 14:56:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 3818321 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2F4A0BF540 for ; Wed, 12 Mar 2014 14:59:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 40F88201BB for ; Wed, 12 Mar 2014 14:59:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3AD0D201BA for ; Wed, 12 Mar 2014 14:58:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754706AbaCLO66 (ORCPT ); Wed, 12 Mar 2014 10:58:58 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:49861 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754449AbaCLO65 (ORCPT ); Wed, 12 Mar 2014 10:58:57 -0400 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N2B008X8WA86O10@mailout4.samsung.com>; Wed, 12 Mar 2014 23:58:56 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.123]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 3B.37.12635.F2670235; Wed, 12 Mar 2014 23:58:56 +0900 (KST) X-AuditID: cbfee68d-b7fcd6d00000315b-63-5320762f73e9 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 21.D8.28157.F2670235; Wed, 12 Mar 2014 23:58:55 +0900 (KST) Received: from localhost.localdomain ([107.108.83.245]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N2B007I0W7MNG50@mmp1.samsung.com>; Wed, 12 Mar 2014 23:58:55 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, r.sh.open@gmail.com, pankaj.dubey@samsung.com, Rahul Sharma , Arun Kumar K Subject: [PATCH v5 2/5] clk/samsung: add support for pll2550xx Date: Wed, 12 Mar 2014 20:26:45 +0530 Message-id: <1394636208-3125-3-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1394636208-3125-1-git-send-email-rahul.sharma@samsung.com> References: <1394636208-3125-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42JZI2JSrWtQphBscGoak8XHU7dZLeYfOcdq 8X3XF3aL3gVX2Sw2Pb7GajHj/D4mi6cTLrJZLNoKlFj4It5iyqLDrBardv1hdOD22DnrLrvH nWt72Dw2L6n36NuyitHj8ya5ANYoLpuU1JzMstQifbsEroxjJ5qYCzpVK5buvsXcwHhLrouR k0NCwETi/9UDLBC2mMSFe+vZuhi5OIQEljJKbOs5yQxT9GJ7OwtEYhGjxJu228wQTjuTxIbp E8Gq2AR0JWYffMbYxcjBISKQKbFxSy5IDbPALUaJc4+OMYLUCAvYSbT+f84EYrMIqEq8W7CK HcTmFXCX6OpYzQTSKyGgIDFnkg1ImFPAQ+LE4V2sILYQUMmM42dZQWZKCOxjl/jY/x5qjoDE t8mHWCB6ZSU2HYA6WlLi4IobLBMYhRcwMqxiFE0tSC4oTkovMtQrTswtLs1L10vOz93ECIyF 0/+e9e5gvH3A+hBjMtC4icxSosn5wFjKK4k3NDYzsjA1MTU2Mrc0I01YSZw36WFSkJBAemJJ anZqakFqUXxRaU5q8SFGJg5OqQZG5czl/o0Jdp5cu7NK16VqZ25q2/R7//MzTbs09uxc7PKf y2NHY5xjTHIX65R6CTaNtlPir0yc5+222LSqxkWPM2OPdnhSxl+X8F/vXffGGrgZnnnClh1p +Nyoar/EzhWBagz/an5a6yRIsW++m5RWohNTU1F9LEpG7txs17CP19Rf93L2JCmxFGckGmox FxUnAgAuXMuBmwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrKIsWRmVeSWpSXmKPExsVy+t9jAV39MoVgg+8zTCw+nrrNajH/yDlW i++7vrBb9C64ymax6fE1VosZ5/cxWTydcJHNYtFWoMTCF/EWUxYdZrVYtesPowO3x85Zd9k9 7lzbw+axeUm9R9+WVYwenzfJBbBGNTDaZKQmpqQWKaTmJeenZOal2yp5B8c7x5uaGRjqGlpa mCsp5CXmptoqufgE6Lpl5gBdpqRQlphTChQKSCwuVtK3wzQhNMRN1wKmMULXNyQIrsfIAA0k rGHMOHaiibmgU7Vi6e5bzA2Mt+S6GDk5JARMJF5sb2eBsMUkLtxbz9bFyMUhJLCIUeJN221m CKedSWLD9InMIFVsAroSsw8+Y+xi5OAQEciU2LglF6SGWeAWo8S5R8cYQWqEBewkWv8/ZwKx WQRUJd4tWMUOYvMKuEt0daxmAumVEFCQmDPJBiTMKeAhceLwLlYQWwioZMbxs6wTGHkXMDKs YhRNLUguKE5KzzXSK07MLS7NS9dLzs/dxAiOtGfSOxhXNVgcYhTgYFTi4V2oKR8sxJpYVlyZ e4hRgoNZSYT3aaFCsBBvSmJlVWpRfnxRaU5q8SHGZKCjJjJLiSbnA5NAXkm8obGJuamxqaWJ hYmZJWnCSuK8B1utA4UE0hNLUrNTUwtSi2C2MHFwSjUw6sm6OnPfm2Qbu+lA57I9ixmbT73o fuGaYOu2MSQ80/SMvrHv4fU//5y7NfvEhXkftn2Rk73K6lx5Rd80jCWaYc56m1t2Vm9l2Db1 PJNljf3BUiFwwnGro/GswxtPSMm8u+T0RWuH5otXMRvY9801f2JkN2v1AqMJ2YvcuNW8b6Ys PTs5b0vRdyWW4oxEQy3mouJEAGXgZYf4AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Pankaj Dubey exynos5260 use pll2550xx and it has different bit fields for P,M,S values as compared to pll2550. Support for pll2550xx is added here. Signed-off-by: Pankaj Dubey Signed-off-by: Rahul Sharma Signed-off-by: Arun Kumar K --- drivers/clk/samsung/clk-pll.c | 108 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 109 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 1f310be..18e42ef 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -947,6 +947,108 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, return clk; } +/* + * PLL2550xx Clock Type + */ + +/* Maximum lock time can be 270 * PDIV cycles */ +#define PLL2550XX_LOCK_FACTOR 270 + +#define PLL2550XX_M_MASK 0x3FF +#define PLL2550XX_P_MASK 0x3F +#define PLL2550XX_S_MASK 0x7 +#define PLL2550XX_LOCK_STAT_MASK 0x1 +#define PLL2550XX_M_SHIFT 9 +#define PLL2550XX_P_SHIFT 3 +#define PLL2550XX_S_SHIFT 0 +#define PLL2550XX_LOCK_STAT_SHIFT 21 + +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, pll_con; + u64 fvco = parent_rate; + + pll_con = __raw_readl(pll->con_reg); + mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; + pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; + sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) +{ + u32 old_mdiv, old_pdiv; + + old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; + old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; + + return mdiv != old_mdiv || pdiv != old_pdiv; +} + +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 tmp; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + tmp = __raw_readl(pll->con_reg); + + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { + /* If only s change, change just s value only*/ + tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT); + tmp |= rate->sdiv << PLL2550XX_S_SHIFT; + __raw_writel(tmp, pll->con_reg); + + return 0; + } + + /* Set PLL lock time. */ + __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); + + /* Change PLL PMS values */ + tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) | + (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) | + (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT)); + tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | + (rate->pdiv << PLL2550XX_P_SHIFT) | + (rate->sdiv << PLL2550XX_S_SHIFT); + __raw_writel(tmp, pll->con_reg); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK + << PLL2550XX_LOCK_STAT_SHIFT))); + + return 0; +} + +static const struct clk_ops samsung_pll2550xx_clk_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll2550xx_set_rate, +}; + +static const struct clk_ops samsung_pll2550xx_clk_min_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, struct samsung_pll_clock *pll_clk, void __iomem *base) @@ -1049,6 +1151,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_s3c2440_mpll_clk_ops; break; + case pll_2550xx: + if (!pll->rate_table) + init.ops = &samsung_pll2550xx_clk_min_ops; + else + init.ops = &samsung_pll2550xx_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 6428bcc..ec4bc1d 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -31,6 +31,7 @@ enum samsung_pll_type { pll_s3c2410_mpll, pll_s3c2410_upll, pll_s3c2440_mpll, + pll_2550xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \