From patchwork Fri Mar 14 12:53:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 3832821 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DC49B9F2BB for ; Fri, 14 Mar 2014 13:00:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F1C452012F for ; Fri, 14 Mar 2014 13:00:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8B5BE20136 for ; Fri, 14 Mar 2014 13:00:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754502AbaCNNAI (ORCPT ); Fri, 14 Mar 2014 09:00:08 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:33679 "EHLO mail-pa0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754350AbaCNNAH (ORCPT ); Fri, 14 Mar 2014 09:00:07 -0400 Received: by mail-pa0-f54.google.com with SMTP id lf10so2611478pab.13 for ; Fri, 14 Mar 2014 06:00:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=pLzYoDah96g5ceOLvdh7DpdTMrOgP2ncW42ea1rx66I=; b=lb8KA4rk0vEEnz/izWZUCV4UR5M4UUeigkh9X831HCP4a+nGzjcJz5RAiKBZznQQCB 2OzmqDtdyjm5k8ps7sCtZ8WsC+ZCEWSOXjUsm00t0s3aszTmvqDVE+mGkQn1czEmjlnc EX8V+jKFu5qbjLj1i2cmUX5WIs/XxQ/wpjfFIMTfiDIbFPngjUURAvDzEQQiuqcuVAy9 rDSYVtOmZfPgSVTboL4iScHXHWMHUprGoxVywEKHNuw//fGAoggExBdSAMa+8HcUUkqo /PwnTtgh8NgsPkiBbrvLKty+eWlPKD0UFZnUnwaJmBn8LINCv9jmdpa9BljrKncxXyxP 0/pQ== X-Gm-Message-State: ALoCoQlhp1t2mrLRbGCh4VaYV1MA+qIScB+MpGG40CNXSEhKQ1UinMBNKUkp9xVN4XPWetbmWgV4 X-Received: by 10.67.13.134 with SMTP id ey6mr9150644pad.44.1394802006827; Fri, 14 Mar 2014 06:00:06 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id yk4sm16525301pbc.16.2014.03.14.06.00.04 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 14 Mar 2014 06:00:06 -0700 (PDT) From: Sachin Kamat To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, t.figa@samsung.com, mturquette@linaro.org, sachin.kamat@linaro.org Subject: [PATCH 1/1] clk: exynos5420: Register APLL rate table Date: Fri, 14 Mar 2014 18:23:54 +0530 Message-Id: <1394801634-887-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Register APLL rate table in Exynos5420 clock driver. Will be required for the CPUFreq driver. Signed-off-by: Sachin Kamat --- drivers/clk/samsung/clk-exynos5420.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 7fd6bea467fd..358513724adc 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -775,6 +775,30 @@ static struct of_device_id ext_clk_match[] __initdata = { { }, }; +static const struct samsung_pll_rate_table apll_24mhz_tbl[] = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(2000000000, 250, 3, 0), + PLL_35XX_RATE(1900000000, 475, 6, 0), + PLL_35XX_RATE(1800000000, 225, 3, 0), + PLL_35XX_RATE(1700000000, 425, 6, 0), + PLL_35XX_RATE(1600000000, 200, 3, 0), + PLL_35XX_RATE(1500000000, 250, 4, 0), + PLL_35XX_RATE(1400000000, 175, 3, 0), + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 200, 2, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(900000000, 150, 2, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(600000000, 200, 2, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(300000000, 200, 2, 3), + PLL_35XX_RATE(200000000, 200, 3, 3), +}; + /* register exynos5420 clocks */ static void __init exynos5420_clk_init(struct device_node *np) { @@ -790,6 +814,10 @@ static void __init exynos5420_clk_init(struct device_node *np) samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), ext_clk_match); + + if (_get_rate("fin_pll") == 24 * MHZ) + exynos5420_plls[apll].rate_table = apll_24mhz_tbl; + samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), reg_base); samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,