From patchwork Thu Mar 27 11:07:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaik Ameer Basha X-Patchwork-Id: 3897471 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D4BC99F370 for ; Thu, 27 Mar 2014 11:08:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 066EA20203 for ; Thu, 27 Mar 2014 11:08:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 139FA201BA for ; Thu, 27 Mar 2014 11:08:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755282AbaC0LIJ (ORCPT ); Thu, 27 Mar 2014 07:08:09 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:33533 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755221AbaC0LIA (ORCPT ); Thu, 27 Mar 2014 07:08:00 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N3300KYPDLAWR50@mailout4.samsung.com>; Thu, 27 Mar 2014 20:07:58 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.126]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 91.F0.14803.E8604335; Thu, 27 Mar 2014 20:07:58 +0900 (KST) X-AuditID: cbfee691-b7efc6d0000039d3-29-5334068e3122 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id B4.46.28157.E8604335; Thu, 27 Mar 2014 20:07:58 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N3300B8BDKNRG30@mmp1.samsung.com>; Thu, 27 Mar 2014 20:07:58 +0900 (KST) From: Shaik Ameer Basha To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, shaik.samsung@gmail.com, r.sh.open@gmail.com, Rahul Sharma , Shaik Ameer Basha Subject: [PATCH v2 2/7] clk: exynos5420: Add more clock IDs Date: Thu, 27 Mar 2014 16:37:45 +0530 Message-id: <1395918470-16374-3-git-send-email-shaik.ameer@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1395918470-16374-1-git-send-email-shaik.ameer@samsung.com> References: <1395918470-16374-1-git-send-email-shaik.ameer@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpnkeLIzCtJLcpLzFFi42JZI2JSp9vHZhJssHaansX8I+dYLb7v+sJu 0bvgKpvFpsfXWC1mnN/HZPF0wkU2i4Uv4i2mLDrManHk4W52i3U7J7FbrNr1h9GB22PnrLvs Hneu7WHz2Lyk3qNvyypGj8+b5AJYo7hsUlJzMstSi/TtErgydm18z1awXaqiu20lSwPjYrEu Rk4OCQETie0tzcwQtpjEhXvr2boYuTiEBJYySjRsa2XqYuQAK1r7lh8ivohRYv+3+8wQzgQm ibcTdoN1swkYSmy/d4UVpEFEIFNi45ZckBpmgSeMEvd397OC1AgLWEu8+7MGrJ5FQFXixK7/ YHFeAXeJd1s62CGWKUjMmWQDEuYU8JCYc+4yWIkQUEnDmlVgx0kI7GKXePfoGCPEHAGJb5MP sUD0ykpsOgD1jKTEwRU3WCYwCi9gZFjFKJpakFxQnJReZKpXnJhbXJqXrpecn7uJERgJp/89 m7iD8f4B60OMyUDjJjJLiSbnAyMpryTe0NjMyMLUxNTYyNzSjDRhJXHe9EdJQUIC6Yklqdmp qQWpRfFFpTmpxYcYmTg4pRoYg75wcrzSylp8Xf3YTGG7fRNLHva9WJl0LXSm3fOKBy8NbufX H3exebNOfWmstV4Ji1fD8Wkv/rJwW/StCdmUJFwd7W9l3p2acYz9g82jaU6z5k/ZIrnoTWrT odk2K51ea2kYC8z4HXZzq/ejvdpz5O9xmD7WFxN4f/gZo5J++lH+FylPLhV2KbEUZyQaajEX FScCAO3W9RKaAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCIsWRmVeSWpSXmKPExsVy+t9jAd0+NpNgg93/lCzmHznHavF91xd2 i94FV9ksNj2+xmox4/w+JounEy6yWSx8EW8xZdFhVosjD3ezW6zbOYndYtWuP4wO3B47Z91l 97hzbQ+bx+Yl9R59W1YxenzeJBfAGtXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGto aWGupJCXmJtqq+TiE6DrlpkDdJmSQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0 kLCGMWPXxvdsBdulKrrbVrI0MC4W62Lk4JAQMJFY+5a/i5ETyBSTuHBvPVsXIxeHkMAiRon9 3+4zQzgTmCTeTtjNDFLFJmAosf3eFVaQZhGBTImNW3JBapgFnjBK3N/dzwpSIyxgLfHuzxqw ehYBVYkTu/6DxXkF3CXebelgh1isIDFnkg1ImFPAQ2LOuctgJUJAJQ1rVrFNYORdwMiwilE0 tSC5oDgpPddIrzgxt7g0L10vOT93EyM4zp5J72Bc1WBxiFGAg1GJh3fHfaNgIdbEsuLK3EOM EhzMSiK8/X+Ng4V4UxIrq1KL8uOLSnNSiw8xJgMdNZFZSjQ5H5gC8kriDY1NzE2NTS1NLEzM LEkTVhLnPdhqHSgkkJ5YkpqdmlqQWgSzhYmDU6qBsWL5A7PpEeEJbO9ipzswnn3CfaH+V84C jfo+hkV6izmeGSe+LmDPPWjw+kTSPI2Wsq/rUx84L15YtejrEzb1xtVTFv037XYW38Cfu19O YL7L0ZzopX3H9mxUtf966u7LMyebVaS+8GSuktpecnhzSXXvse7c+16mN8L5V985/+5OlPh9 r/tyUUosxRmJhlrMRcWJAEVD+Dj3AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rahul Sharma Add more clock IDs to be used in DT bindings for Exynos5420. Signed-off-by: Rahul Sharma Signed-off-by: Shaik Ameer Basha --- include/dt-bindings/clock/exynos5420.h | 62 ++++++++++++++++++++++++++++++-- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 5eefd88..e921913 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -58,6 +58,16 @@ #define CLK_SCLK_GSCL_WA 156 #define CLK_SCLK_GSCL_WB 157 #define CLK_SCLK_HDMIPHY 158 +#define CLK_SCLK_MPHY_REFCLK 159 +#define CLK_SCLK_SPI0_ISP 160 +#define CLK_SCLK_SPI1_ISP 161 +#define CLK_SCLK_UART_ISP 162 +#define CLK_SCLK_ISP_SENSOR0 163 +#define CLK_SCLK_ISP_SENSOR1 164 +#define CLK_SCLK_ISP_SENSOR2 165 +#define CLK_SCLK_PWM_ISP 166 +#define CLK_SCLK_HSIC_12M 167 +#define CLK_SCLK_MPHY_IXTAL24 168 /* gate clocks */ #define CLK_ACLK66_PERIC 256 @@ -123,6 +133,7 @@ #define CLK_USBH20 365 #define CLK_USBD300 366 #define CLK_USBD301 367 +#define CLK_PCLK200_FSYS 370 #define CLK_ACLK400_MSCL 380 #define CLK_MSCL0 381 #define CLK_MSCL1 382 @@ -141,6 +152,8 @@ #define CLK_ACLK300_DISP1 420 #define CLK_FIMD1 421 #define CLK_SMMU_FIMD1 422 +#define CLK_SMMU_FIMD1M1 423 +#define CLK_ACLK400_DISP1 424 #define CLK_ACLK166 430 #define CLK_MIXER 431 #define CLK_ACLK266 440 @@ -172,12 +185,57 @@ #define CLK_SMMU_FIMCL1 493 #define CLK_SMMU_FIMCL3 494 #define CLK_FIMC_LITE3 495 -#define CLK_ACLK_G3D 500 -#define CLK_G3D 501 +#define CLK_G3D 500 #define CLK_SMMU_MIXER 502 +#define CLK_PCLK_TZPC10 503 +#define CLK_PCLK_TZPC11 504 +#define CLK_PCLK_MC 505 +#define CLK_PCLK_TOP_RTC 506 +#define CLK_SMMU_JPEG2 507 +#define CLK_PCLK_ROTATOR 508 +#define CLK_SMMU_RTIC 509 +#define CLK_PCLK_G2D 510 +#define CLK_ACLK_SMMU_G2D 511 +#define CLK_SMMU_G2D 512 +#define CLK_ACLK_SMMU_MDMA0 513 +#define CLK_SMMU_MDMA0 514 +#define CLK_ACLK_SMMU_SSS 515 +#define CLK_SMMU_SSS 516 +#define CLK_SMMU_SLIM_SSS 517 +#define CLK_ACLK_SMMU_SLIM_SSS 518 +#define CLK_ACLK266_ISP 519 +#define CLK_ACLK400_ISP 520 +#define CLK_ACLK333_432_ISP0 521 +#define CLK_ACLK333_432_ISP 522 +#define CLK_ACLK_SMMU_MIXER 523 +#define CLK_PCLK_HDMIPHY 524 +#define CLK_PCLK_GSCL0 525 +#define CLK_PCLK_GSCL1 526 +#define CLK_PCLK_FIMC_3AA 527 +#define CLK_ACLK_FIMC_LITE0 528 +#define CLK_ACLK_FIMC_LITE1 529 +#define CLK_PCLK_FIMC_LITE0 530 +#define CLK_PCLK_FIMC_LITE1 531 +#define CLK_PCLK_FIMC_LITE3 532 +#define CLK_PCLK_MSCL0 533 +#define CLK_PCLK_MSCL1 534 +#define CLK_PCLK_MSCL2 535 +#define CLK_PCLK_MFC 536 /* mux clocks */ #define CLK_MOUT_HDMI 640 +#define CLK_MOUT_FIMD1 641 +#define CLK_MOUT_MAUDIO0 642 +#define CLK_MOUT_SPI0 643 +#define CLK_MOUT_SPI1 644 +#define CLK_MOUT_SPI2 645 +#define CLK_MOUT_SW_ACLK333 646 +#define CLK_MOUT_USER_ACLK333 647 +#define CLK_MOUT_SW_ACLK300_GSCL 648 +#define CLK_MOUT_USER_ACLK300_GSCL 649 +#define CLK_MOUT_SW_ACLK333_432_GSCL 650 +#define CLK_MOUT_USER_ACLK333_432_GSCL 651 +#define CLK_MOUT_G3D 652 /* divider clocks */ #define CLK_DOUT_PIXEL 768