From patchwork Wed Apr 2 08:24:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Dubey X-Patchwork-Id: 3927241 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8370FBF540 for ; Wed, 2 Apr 2014 08:10:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 18C5220240 for ; Wed, 2 Apr 2014 08:10:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6F39B201F7 for ; Wed, 2 Apr 2014 08:10:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758030AbaDBIJT (ORCPT ); Wed, 2 Apr 2014 04:09:19 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:14554 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752937AbaDBIHk (ORCPT ); Wed, 2 Apr 2014 04:07:40 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N3E009ZD98NI5C0@mailout1.samsung.com>; Wed, 02 Apr 2014 17:07:36 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.50]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 53.94.14803.745CB335; Wed, 02 Apr 2014 17:07:35 +0900 (KST) X-AuditID: cbfee691-b7efc6d0000039d3-96-533bc547d522 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id EC.41.28157.745CB335; Wed, 02 Apr 2014 17:07:35 +0900 (KST) Received: from localhost.localdomain ([12.36.165.191]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N3E00EIG98HYT50@mmp2.samsung.com>; Wed, 02 Apr 2014 17:07:35 +0900 (KST) From: Pankaj Dubey To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, linux@arm.linux.org.uk, chow.kim@samsung.com, Pankaj Dubey Subject: [RFC PATCH 2/2] ARM: EXYNOS: remove arch specific PMU implementation Date: Wed, 02 Apr 2014 17:24:45 +0900 Message-id: <1396427085-4696-3-git-send-email-pankaj.dubey@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1396427085-4696-1-git-send-email-pankaj.dubey@samsung.com> References: <1396427085-4696-1-git-send-email-pankaj.dubey@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHLMWRmVeSWpSXmKPExsVy+t8zI133o9bBBsd/Wlgsm3SXzaJ3wVU2 i02Pr7FaXN41h81ixvl9TBa3L/NaLNr6hd2B3aOluYfNY/OSeo++LasYPT5vkgtgieKySUnN ySxLLdK3S+DKmPZ+KWvBvmWMFa/fTWdpYNzZztjFyMkhIWAisfL8cmYIW0ziwr31bCC2kMAy RoltzRxdjBxgNYeP63UxcgGFpzNKnJq2mwWipo1JYultSRCbTUBX4sn7uWBzRASyJS7NugVW wyxQJPFm3R+wmcICvhJPPz1gArFZBFQlpj65CGbzCrhLfJ/9hB1il4LEnEk2IGFOAQ+J79Pm M0Kscpe48PcoE8gNEgLT2SW+rJ3PCjFHQOLb5EMsEL2yEpsOQL0iKXFwxQ2WCYzCCxgZVjGK phYkFxQnpReZ6hUn5haX5qXrJefnbmKEhPXEHYz3D1gfYkwGGjeRWUo0OR8YF3kl8YbGZkYW piamxkbmlmakCSuJ86Y/SgoSEkhPLEnNTk0tSC2KLyrNSS0+xMjEwSnVwFgfZhT99sS0O+dW O+x2Opi7QHBy3/fLdpJHywWcXufc2/VD/fDqiuriLSfKGw6ePeUYXCI143jqyTULPhUvLLVg Ef3RXWawVlD5QBtbkJRj5OyLO3duTt40xYx/wg29WKOK5OjcmF0KHUcmSs3avdpnzQthHad3 TLa3tldXqDb9rvTac+B4pp8SS3FGoqEWc1FxIgCAynXGgQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrDIsWRmVeSWpSXmKPExsVy+t9jQV33o9bBBke69C2WTbrLZtG74Cqb xabH11gtLu+aw2Yx4/w+Jovbl3ktFm39wu7A7tHS3MPmsXlJvUffllWMHp83yQWwRDUw2mSk JqakFimk5iXnp2TmpdsqeQfHO8ebmhkY6hpaWpgrKeQl5qbaKrn4BOi6ZeYAHaCkUJaYUwoU CkgsLlbSt8M0ITTETdcCpjFC1zckCK7HyAANJKxjzJj2filrwb5ljBWv301naWDc2c7YxcjB ISFgInH4uF4XIyeQKSZx4d56ti5GLg4hgemMEqem7WYBSQgJtDFJLL0tCWKzCehKPHk/lxnE FhHIlrg06xZYDbNAkcSbdX/YQGxhAV+Jp58eMIHYLAKqElOfXASzeQXcJb7PfsIOsVdBYs4k G5Awp4CHxPdp8xkhVrlLXPh7lGkCI+8CRoZVjKKpBckFxUnpuUZ6xYm5xaV56XrJ+bmbGMFx 80x6B+OqBotDjAIcjEo8vAfOWwULsSaWFVfmHmKU4GBWEuHlOmgdLMSbklhZlVqUH19UmpNa fIgxGeioicxSosn5wJjOK4k3NDYxM7I0MrMwMjE3J01YSZz3YKt1oJBAemJJanZqakFqEcwW Jg5OqQbGmOcv7PZt/cF601rw3Rc1t5cPjM9b+d6PUjK703GkXka0aemtu7wBa/cLS8YYdjuq LYnnje2IffDyaMbqus6f+clp63fcTbwqW1F+Ylv/xR9vttgnzJP8zSZ+cebD/p6QnKSmd3JX 9fTy5e245X1Ed8gYpi4Ue6Llz/nI20PunMOqdfwuK7YqsRRnJBpqMRcVJwIAyoeuE98CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY, UPPERCASE_50_75 autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Pankaj Dubey --- arch/arm/mach-exynos/Kconfig | 2 + arch/arm/mach-exynos/Makefile | 2 - arch/arm/mach-exynos/pmu.c | 426 ----------------------------------------- 3 files changed, 2 insertions(+), 428 deletions(-) delete mode 100644 arch/arm/mach-exynos/pmu.c diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index fcd78c2..61f0ead 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -26,6 +26,7 @@ config ARCH_EXYNOS4 select PINCTRL select PM_GENERIC_DOMAINS if PM_RUNTIME select S5P_DEV_MFC + select MFD_EXYNOS_PMU help Samsung EXYNOS4 SoCs based systems @@ -37,6 +38,7 @@ config ARCH_EXYNOS5 select HAVE_SMP select PINCTRL select USB_ARCH_HAS_XHCI + select MFD_EXYNOS_PMU help Samsung EXYNOS5 (Cortex-A15) SoC based systems diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index a656dbe..19fdf17 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -18,8 +18,6 @@ obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o -obj-$(CONFIG_ARCH_EXYNOS) += pmu.o - obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c deleted file mode 100644 index 30b20ab..0000000 --- a/arch/arm/mach-exynos/pmu.c +++ /dev/null @@ -1,426 +0,0 @@ -/* - * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * EXYNOS - CPU PMU(Power Management Unit) support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include - -#include - -#include "common.h" - -static const struct exynos_pmu_conf *exynos_pmu_config; -static void __iomem *pmu_base; - -static const struct exynos_pmu_conf exynos4210_pmu_config[] = { - /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ - { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } }, - { S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } }, - { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } }, - { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } }, - { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, - { PMU_TABLE_END,}, -}; - -static const struct exynos_pmu_conf exynos4x12_pmu_config[] = { - { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } }, - { S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } }, - /* XXX_OPTION register should be set other field */ - { S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } }, - { S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } }, - { S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } }, - { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } }, - { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } }, - { S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } }, - { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } }, - { S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } }, - { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, - { PMU_TABLE_END,}, -}; - -static const struct exynos_pmu_conf exynos4412_pmu_config[] = { - { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } }, - { PMU_TABLE_END,}, -}; - -static const struct exynos_pmu_conf exynos5250_pmu_config[] = { - /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ - { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, - { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, - { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, - { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, - { EXYNOS5_ARM_L2_OPTION, { 0x10, 0x10, 0x0 } }, - { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, - { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, - { EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { PMU_TABLE_END,}, -}; - -static unsigned int const exynos5_list_both_cnt_feed[] = { - EXYNOS5_ARM_CORE0_OPTION, - EXYNOS5_ARM_CORE1_OPTION, - EXYNOS5_ARM_COMMON_OPTION, - EXYNOS5_GSCL_OPTION, - EXYNOS5_ISP_OPTION, - EXYNOS5_MFC_OPTION, - EXYNOS5_G3D_OPTION, - EXYNOS5_DISP1_OPTION, - EXYNOS5_MAU_OPTION, - EXYNOS5_TOP_PWR_OPTION, - EXYNOS5_TOP_PWR_SYSMEM_OPTION, -}; - -static unsigned int const exynos5_list_diable_wfi_wfe[] = { - EXYNOS5_ARM_CORE1_OPTION, - EXYNOS5_FSYS_ARM_OPTION, - EXYNOS5_ISP_ARM_OPTION, -}; - -static void exynos5_init_pmu(void) -{ - unsigned int i; - unsigned int tmp; - - /* - * Enable both SC_FEEDBACK and SC_COUNTER - */ - for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) { - tmp = __raw_readl(pmu_base + exynos5_list_both_cnt_feed[i]); - tmp |= (EXYNOS5_USE_SC_FEEDBACK | - EXYNOS5_USE_SC_COUNTER); - __raw_writel(tmp, pmu_base + exynos5_list_both_cnt_feed[i]); - } - - /* - * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable - */ - tmp = __raw_readl(pmu_base + EXYNOS5_ARM_COMMON_OPTION); - tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; - __raw_writel(tmp, pmu_base + EXYNOS5_ARM_COMMON_OPTION); - - /* - * Disable WFI/WFE on XXX_OPTION - */ - for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) { - tmp = __raw_readl(pmu_base + exynos5_list_diable_wfi_wfe[i]); - tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE | - EXYNOS5_OPTION_USE_STANDBYWFI); - __raw_writel(tmp, pmu_base + exynos5_list_diable_wfi_wfe[i]); - } -} - -void exynos_sys_powerdown_conf(enum sys_powerdown mode) -{ - unsigned int i; - - if (soc_is_exynos5250()) - exynos5_init_pmu(); - - for (i = 0; (exynos_pmu_config[i].offset != PMU_TABLE_END) ; i++) - __raw_writel(exynos_pmu_config[i].val[mode], - pmu_base + exynos_pmu_config[i].offset); - - if (soc_is_exynos4412()) { - for (i = 0; exynos4412_pmu_config[i].offset != PMU_TABLE_END; i++) - __raw_writel(exynos4412_pmu_config[i].val[mode], - pmu_base + exynos4412_pmu_config[i].offset); - } -} - -static int __init exynos_pmu_init(void) -{ - unsigned int value; - - exynos_pmu_config = exynos4210_pmu_config; - pmu_base = get_exynos_pmubase(); - - if (soc_is_exynos4210()) { - exynos_pmu_config = exynos4210_pmu_config; - pr_info("EXYNOS4210 PMU Initialize\n"); - } else if (soc_is_exynos4212() || soc_is_exynos4412()) { - exynos_pmu_config = exynos4x12_pmu_config; - pr_info("EXYNOS4x12 PMU Initialize\n"); - } else if (soc_is_exynos5250()) { - /* - * When SYS_WDTRESET is set, watchdog timer reset request - * is ignored by power management unit. - */ - value = __raw_readl(pmu_base + EXYNOS5_AUTO_WDTRESET_DISABLE); - value &= ~EXYNOS5_SYS_WDTRESET; - __raw_writel(value, pmu_base + EXYNOS5_AUTO_WDTRESET_DISABLE); - - value = __raw_readl(pmu_base + EXYNOS5_MASK_WDTRESET_REQUEST); - value &= ~EXYNOS5_SYS_WDTRESET; - __raw_writel(value, pmu_base + EXYNOS5_MASK_WDTRESET_REQUEST); - - exynos_pmu_config = exynos5250_pmu_config; - pr_info("EXYNOS5250 PMU Initialize\n"); - } else { - pr_info("EXYNOS: PMU not supported\n"); - } - - return 0; -} -arch_initcall(exynos_pmu_init);