From patchwork Mon Apr 21 06:45:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Kumar K X-Patchwork-Id: 4022791 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BA89F9F44A for ; Mon, 21 Apr 2014 06:45:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B885320265 for ; Mon, 21 Apr 2014 06:45:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AAD772025B for ; Mon, 21 Apr 2014 06:45:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751285AbaDUGpg (ORCPT ); Mon, 21 Apr 2014 02:45:36 -0400 Received: from mail-pb0-f42.google.com ([209.85.160.42]:36520 "EHLO mail-pb0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751269AbaDUGpd (ORCPT ); Mon, 21 Apr 2014 02:45:33 -0400 Received: by mail-pb0-f42.google.com with SMTP id rr13so3466782pbb.1 for ; Sun, 20 Apr 2014 23:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=O0SEi67qvkeR5VayI7T+xjKQIfqocLnfeKVswybhD3M=; b=Km2SGxCloUTvb0Pmtp/pSmsm5FqsitrOHqveZR6i9OzLkFtalKdDCkrC2wG0mw3Ru0 gx/Ajx1c1QcPcEwEVANNfvOteQAyo+h/w35KMup2A5m3LWsTdjyNSLVu+RaMmcW5hhY0 lYf5b0sRWYfTJX07jaEbkY8e6a7WCw5sv1EiZbGOP2aC3QIYKcZ0Apai2Y7ccCT8P40M AFanOo3W1qMfahzBi4HyKDxzOeOIL2YxBm64HlbxtbMC/wH7Rskks0Q21eC6M8G2t9Bk Be2zSBjsYRIicpKRjj06Ats/smKF3EDYZAB3X8ARc3GRg1e5tGq7Oov7kh5d1mpp7UPb YKbQ== X-Received: by 10.66.122.36 with SMTP id lp4mr36417525pab.82.1398062732366; Sun, 20 Apr 2014 23:45:32 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id xx4sm6270453pbb.51.2014.04.20.23.45.29 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 20 Apr 2014 23:45:31 -0700 (PDT) From: Arun Kumar K To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: kgene.kim@samsung.com, dianders@chromium.org, alim.akhtar@samsung.com, tomasz.figa@gmail.com, olofj@google.com, arunkk.samsung@gmail.com Subject: [PATCH 4/4] ARM: dts: Add peach-pi board support Date: Mon, 21 Apr 2014 12:15:12 +0530 Message-Id: <1398062712-28602-5-git-send-email-arun.kk@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398062712-28602-1-git-send-email-arun.kk@samsung.com> References: <1398062712-28602-1-git-send-email-arun.kk@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds support for google peach-pi board having the Exynos5800 SoC. Signed-off-by: Arun Kumar K Signed-off-by: Doug Anderson --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/exynos5800-peach-pi.dts | 225 +++++++++++++++++++++++++++++ 2 files changed, 227 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/exynos5800-peach-pi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c17cf4b..6ed6467 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -77,7 +77,8 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5420-smdk5420.dtb \ exynos5420-peach-pit.dtb \ exynos5440-sd5v1.dtb \ - exynos5440-ssdk5440.dtb + exynos5440-ssdk5440.dtb \ + exynos5800-peach-pi.dtb dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ecx-2000.dtb diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts new file mode 100644 index 0000000..3ea6c8a --- /dev/null +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -0,0 +1,225 @@ +/* + * Google Peach Pi Rev 10+ board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include +#include "exynos5800.dtsi" + +/ { + model = "Google Peach Pi Rev 10+"; + + compatible = "google,pi-rev16", + "google,pi-rev15", "google,pi-rev14", + "google,pi-rev13", "google,pi-rev12", + "google,pi-rev11", "google,pi-rev10", + "google,pi", "google,peach", "samsung,exynos5800", + "samsung,exynos5"; + + memory { + reg = <0x20000000 0xE0000000>; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + pinctrl@13400000 { + lid_irq: lid-irq { + samsung,pins = "gpx3-4"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + power_key_irq: power-key-irq { + samsung,pins = "gpx1-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + tpm_irq: tpm-irq { + samsung,pins = "gpx1-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl@14010000 { + spi_flash_cs: spi-flash-cs { + samsung,pins = "gpa2-5"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + backlight_pwm: backlight-pwm { + samsung,pins = "gpb2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&power_key_irq &lid_irq>; + + power { + label = "Power"; + gpios = <&gpx1 2 1>; + linux,code = ; + gpio-key,wakeup; + }; + + lid-switch { + label = "Lid"; + gpios = <&gpx3 4 1>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + gpio-key,wakeup; + }; + }; + + rtc@101E0000 { + status = "okay"; + }; + + serial@12C30000 { + status = "okay"; + }; + + mmc@12200000 { + status = "okay"; + num-slots = <1>; + broken-cd; + caps2-mmc-hs200-1_8v; + supports-highspeed; + non-removable; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + mmc@12220000 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + + i2c@12E10000 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + /* Unused irq; but still need to configure the pins */ + pinctrl-names = "default"; + pinctrl-0 = <&tpm_irq>; + + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + }; + + spi@12d30000 { + status = "okay"; + samsung,spi-src-clk = <0>; + num-cs = <1>; + + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_cs>; + + controller-data { + cs-gpio = <&gpa2 5 0>; + samsung,spi-feedback-delay = <2>; + }; + }; + }; + + adc@12D10000 { + ncp15wb473@3 { + compatible = "ntc,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 3>; + }; + ncp15wb473@4 { + compatible = "ntc,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 4>; + }; + ncp15wb473@5 { + compatible = "ntc,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 5>; + }; + ncp15wb473@6 { + compatible = "ntc,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 6>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + default-brightness-level = <2800>; + pinctrl-0 = <&backlight_pwm>; + pinctrl-names = "default"; + }; + + /* + * Use longest HW watchdog in SoC (32 seconds) since the hardware + * watchdog provides no debugging information (compared to soft/hard + * lockup detectors) and so should be last resort. + */ + watchdog@101D0000 { + timeout-sec = <32>; + }; +};