[v12,31/31] ARM: dts: add System MMU nodes of exynos5420

Message ID	1398584283-22846-32-git-send-email-shaik.ameer@samsung.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-samsung-soc-owner@kernel.org> From: Shaik Ameer Basha <shaik.ameer@samsung.com> To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Cc: kgene.kim@samsung.com, tomasz.figa@gmail.com, pullip.cho@samsung.com, a.motakis@virtualopensystems.com, grundler@chromium.org, joro@8bytes.org, prathyush.k@samsung.com, rahul.sharma@samsung.com, sachin.kamat@linaro.org, supash.ramaswamy@linaro.org, Varun.Sethi@freescale.com, s.nawrocki@samsung.com, t.figa@samsung.com, joshi@samsung.com, Shaik Ameer Basha <shaik.ameer@samsung.com> Subject: [PATCH v12 31/31] ARM: dts: add System MMU nodes of exynos5420 Date: Sun, 27 Apr 2014 13:08:03 +0530 Message-id: <1398584283-22846-32-git-send-email-shaik.ameer@samsung.com> In-reply-to: <1398584283-22846-1-git-send-email-shaik.ameer@samsung.com> References: <1398584283-22846-1-git-send-email-shaik.ameer@samsung.com> DLP-Filter: Pass Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c3a9a66..1fc0c9f 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -125,7 +125,7 @@ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; }; - codec@11000000 { + mfc: codec@11000000 { compatible = "samsung,mfc-v7"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; @@ -472,7 +472,7 @@ phy-names = "dp"; }; - fimd@14400000 { + fimd: fimd@14400000 { samsung,power-domain = <&disp_pd>; clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; @@ -644,7 +644,7 @@ status = "disabled"; }; - mixer@14450000 { + mixer: mixer@14450000 { compatible = "samsung,exynos5420-mixer"; reg = <0x14450000 0x10000>; interrupts = <0 94 0>; @@ -732,4 +732,207 @@ clock-names = "secss"; samsung,power-domain = <&g2d_pd>; }; + + sysmmu_g2dr: sysmmu@10A60000 { + compatible = "samsung,sysmmu-v3.2"; + reg = <0x10A60000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + }; + + sysmmu_g2dw: sysmmu@10A70000 { + compatible = "samsung,sysmmu-v3.2"; + reg = <0x10A70000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + }; + + sysmmu_scaler0r: sysmmu@12880000 { + compatible = "samsung,sysmmu-v3.2"; + reg = <0x12880000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + }; + + sysmmu_scaler1r: sysmmu@12890000 { + compatible = "samsung,sysmmu-v3.2"; + reg = <0x12890000 0x1000>; + interrupts = <0 186 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + }; + + sysmmu_scaler2r: sysmmu@128A0000 { + compatible = "samsung,sysmmu-v3.2"; + reg = <0x128A0000 0x1000>; + interrupts = <0 188 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + }; + + sysmmu_scaler0w: sysmmu@128C0000 { + compatible = "samsung,sysmmu-v3.2"; + reg = <0x128C0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <27 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + }; + + sysmmu_scaler1w: sysmmu@128D0000 { + compatible = "samsung,sysmmu-v3.2"; + reg = <0x128D0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <22 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + }; + + sysmmu_scaler2w: sysmmu@128E0000 { + compatible = "samsung,sysmmu-v3.2"; + reg = <0x128E0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <19 6>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + }; + + sysmmu_mfc_l: sysmmu@11200000 { + compatible = "samsung,sysmmu-v2"; + reg = <0x11200000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <8 5>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; + mmu-masters = <&mfc>; + samsung,power-domain = <&mfc_pd>; + }; + + sysmmu_mfc_r: sysmmu@11210000 { + compatible = "samsung,sysmmu-v2"; + reg = <0x11210000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <6 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; + mmu-masters = <&mfc>; + samsung,power-domain = <&mfc_pd>; + }; + + sysmmu_rotator: sysmmu@11D40000 { + compatible = "samsung,sysmmu-v3.1"; + reg = <0x11D40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; + }; + + sysmmu_fimc_lite0: sysmmu@13C40000 { + compatible = "samsung,sysmmu-v3.3"; + reg = <0x13C40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMCL0>, <&clock CLK_FIMC_LITE0>; + samsung,power-domain = <&gsc_pd>; + }; + + sysmmu_fimc_lite1: sysmmu@13C50000 { + compatible = "samsung,sysmmu-v3.3"; + reg = <0x13C50000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <24 1>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMCL1>, <&clock CLK_FIMC_LITE1>; + samsung,power-domain = <&gsc_pd>; + }; + + sysmmu_fimc_lite3: sysmmu@13D50000 { + compatible = "samsung,sysmmu-v1"; + reg = <0x13D50000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMCL3>, <&clock CLK_FIMC_LITE3>; + samsung,power-domain = <&gsc_pd>; + }; + + sysmmu_gsc0: sysmmu@13E80000 { + compatible = "samsung,sysmmu-v3.3"; + reg = <0x13E80000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; + samsung,power-domain = <&gsc_pd>; + mmu-masters = <&gsc_0>; + }; + + sysmmu_gsc1: sysmmu@13E90000 { + compatible = "samsung,sysmmu-v3.3"; + reg = <0x13E90000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <2 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; + samsung,power-domain = <&gsc_pd>; + mmu-masters = <&gsc_1>; + }; + + sysmmu_fimd0w04: sysmmu@14640000 { + compatible = "samsung,sysmmu-v3.3"; + reg = <0x14640000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; + samsung,power-domain = <&disp_pd>; + mmu-masters = <&fimd>; + }; + + sysmmu_fimd0w123: sysmmu@14680000 { + compatible = "samsung,sysmmu-v3.3"; + reg = <0x14680000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <3 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; + samsung,power-domain = <&disp_pd>; + mmu-masters = <&fimd>; + }; + + sysmmu_tv: sysmmu@14650000 { + compatible = "samsung,sysmmu-v3.3"; + reg = <0x14650000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <7 4>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; + samsung,power-domain = <&disp_pd>; + mmu-masters = <&mixer>; + }; + + sysmmu_jpeg: sysmmu@11F10000 { + compatible = "samsung,sysmmu-v1"; + reg = <0x11F10000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 2>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; + }; + + sysmmu_jpeg2: sysmmu@11F20000 { + compatible = "samsung,sysmmu-v1"; + reg = <0x11F20000 0x1000>; + interrupts = <0 169 0>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG2>; + }; };

[v12,31/31] ARM: dts: add System MMU nodes of exynos5420

Commit Message

Patch