From patchwork Mon Apr 28 10:20:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Kumar K X-Patchwork-Id: 4076161 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A127ABFF02 for ; Mon, 28 Apr 2014 10:20:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BD4952028D for ; Mon, 28 Apr 2014 10:20:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6DC9420274 for ; Mon, 28 Apr 2014 10:20:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755209AbaD1KUs (ORCPT ); Mon, 28 Apr 2014 06:20:48 -0400 Received: from mail-pb0-f46.google.com ([209.85.160.46]:59347 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755047AbaD1KUq (ORCPT ); Mon, 28 Apr 2014 06:20:46 -0400 Received: by mail-pb0-f46.google.com with SMTP id ma3so1811283pbc.5 for ; Mon, 28 Apr 2014 03:20:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=2ZMy5dC7U9PUjUmYmss0P+m8j0tivG+gQlu7AKMHi5Y=; b=iV/51H2gtrVokS0ZEWA3doQQyCD6xb2DSNemeTFeXH40TmJpsT68kd0lgRfjXOeSc+ GmEng5f+Yvkp6eoAL73ci51ZSNMyUVyhwNDj9+Wjz4GD9/CJYv9y85cgv0wzLlGsrIJM zu5H7+vG9sQTXkcHBvUM3Va/6azRKa0nStJ6rcak2V/RG0so4Jpwl2A6xOvyKmFw73vX 8sDQ7cK3mRz3yB1WWBeaNh3d+/gI2jUZ6r7wTgNa1pCW4XUL9OVF6Sly2dLvdyRAzkha VcOnSFEZAlCtplyIE/KTUIiOlGyvU7Bayj4Zi9S9Kx/CLr1gy9BL2f0UZGxIFX1E4O7w d83g== X-Received: by 10.68.229.68 with SMTP id so4mr27862742pbc.110.1398680445907; Mon, 28 Apr 2014 03:20:45 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id qh2sm89157119pab.13.2014.04.28.03.20.43 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 28 Apr 2014 03:20:45 -0700 (PDT) From: Arun Kumar K To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, t.figa@samsung.com, kgene.kim@samsung.com, arunkk.samsung@gmail.com Subject: [PATCH] clk: exynos5420: Add clock IDs needed by GPU Date: Mon, 28 Apr 2014 15:50:44 +0530 Message-Id: <1398680444-12400-1-git-send-email-arun.kk@samsung.com> X-Mailer: git-send-email 1.7.9.5 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds IDs for the clocks needed by the ARM Mali GPU in exynos5420. Signed-off-by: Arun Kumar K --- drivers/clk/samsung/clk-exynos5420.c | 4 ++-- include/dt-bindings/clock/exynos5420.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 60b2681..7a9e3b4 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -362,7 +362,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1), MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1), MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1), - MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p, + MUX_A(CLK_MOUT_G3D, "mout_user_aclk_g3d", user_aclk_g3d_p, SRC_TOP5, 16, 1, "aclkg3d"), MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p, SRC_TOP5, 20, 1), @@ -372,7 +372,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { SRC_TOP5, 28, 1), MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1), - MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1), + MUX(CLK_MOUT_VPLL, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1), MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1), MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1), MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1), diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 5eefd88..54db8b3 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -178,6 +178,8 @@ /* mux clocks */ #define CLK_MOUT_HDMI 640 +#define CLK_MOUT_G3D 641 +#define CLK_MOUT_VPLL 642 /* divider clocks */ #define CLK_DOUT_PIXEL 768