diff mbox

[v4,10/15] clk: exynos5420: update clocks for FSYS and FSYS2 blocks

Message ID 1399393610-23394-11-git-send-email-shaik.ameer@samsung.com (mailing list archive)
State New, archived
Headers show

Commit Message

Shaik Ameer Basha May 6, 2014, 4:26 p.m. UTC 
This patch adds more clocks from FSYS and FSYS2 blocks
and uses GATE_IP_* registers for gating IPs.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c |   41 ++++++++++++++++++++++------------
 1 file changed, 27 insertions(+), 14 deletions(-)

Comments

Tomasz Figa May 6, 2014, 5:43 p.m. UTC | #1 
Shaik,

On 06.05.2014 18:26, Shaik Ameer Basha wrote:
> This patch adds more clocks from FSYS and FSYS2 blocks
> and uses GATE_IP_* registers for gating IPs.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
> ---
>   drivers/clk/samsung/clk-exynos5420.c |   41 ++++++++++++++++++++++------------
>   1 file changed, 27 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index f0460b4..6d88ae2 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c

[snip]

> @@ -736,12 +749,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>   	GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
>   		GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
>   	GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
> -		GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
> +		GATE_TOP_SCLK_FSYS, 9, CLK_IGNORE_UNUSED, 0),

Why CLK_IGNORE_UNUSED? Also CLK_SET_RATE_PARENT seems quite right for 
this clock.

>   	GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
> -		GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
> -
> -	GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
> -		SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
> +		GATE_TOP_SCLK_FSYS, 10, CLK_IGNORE_UNUSED, 0),

Same here.

>
>   	/* Display */
>   	GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
> @@ -760,20 +770,23 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>   		GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
>   	GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
>   		GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
> -	/* FSYS */
> +
> +	/* FSYS Block */
>   	GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
>   	GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
>   	GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
>   	GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
> -	GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
> -	GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
> -	GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
> -	GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
> +	GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
> +	GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
> +	GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
> +	GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
>   	GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
> -			GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
> -	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
> -	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
> -	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
> +			GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
> +	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
> +	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
> +	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
> +	GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
> +			GATE_IP_FSYS, 23, CLK_SET_RATE_PARENT, 0),

Gating an SCLK through an GATE_IP_* register looks a bit unusual. The 
original entry for this clock had SRC_MASK_FSYS register used. Also 
there is the GATE_TOP_SCLK_FSYS register, are you sure that there is no 
bit for this clock there?

Best regards,
Tomasz
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Shaik Ameer Basha May 7, 2014, 12:14 p.m. UTC | #2 
Hi Tomasz,


On Tue, May 6, 2014 at 11:13 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Shaik,
>
>
> On 06.05.2014 18:26, Shaik Ameer Basha wrote:
>>
>> This patch adds more clocks from FSYS and FSYS2 blocks
>> and uses GATE_IP_* registers for gating IPs.
>>
>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
>> ---
>>   drivers/clk/samsung/clk-exynos5420.c |   41
>> ++++++++++++++++++++++------------
>>   1 file changed, 27 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c
>> b/drivers/clk/samsung/clk-exynos5420.c
>> index f0460b4..6d88ae2 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>
>
> [snip]
>
>
>> @@ -736,12 +749,9 @@ static struct samsung_gate_clock
>> exynos5420_gate_clks[] __initdata = {
>>         GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
>>                 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
>>         GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
>> -               GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
>> +               GATE_TOP_SCLK_FSYS, 9, CLK_IGNORE_UNUSED, 0),
>
>
> Why CLK_IGNORE_UNUSED? Also CLK_SET_RATE_PARENT seems quite right for this
> clock.

Sorry, that was a hack for some internal USB testing. Some how it got
merged with this series.
I will revert it to CLK_SET_RATE_PARENT.

>
>
>>         GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
>> -               GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
>> -
>> -       GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
>> -               SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
>> +               GATE_TOP_SCLK_FSYS, 10, CLK_IGNORE_UNUSED, 0),
>
>
> Same here.

Same here :)

>
>
>>
>>         /* Display */
>>         GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
>> @@ -760,20 +770,23 @@ static struct samsung_gate_clock
>> exynos5420_gate_clks[] __initdata = {
>>                 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
>>         GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
>>                 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
>> -       /* FSYS */
>> +
>> +       /* FSYS Block */
>>         GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
>>         GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
>>         GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
>>         GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
>> -       GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
>> -       GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
>> -       GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
>> -       GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
>> +       GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
>> +       GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
>> +       GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
>> +       GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
>>         GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
>> -                       GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
>> -       GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0,
>> 0),
>> -       GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21,
>> 0, 0),
>> -       GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28,
>> 0, 0),
>> +                       GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
>> +       GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0,
>> 0),
>> +       GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0,
>> 0),
>> +       GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0,
>> 0),
>> +       GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
>> +                       GATE_IP_FSYS, 23, CLK_SET_RATE_PARENT, 0),
>
>
> Gating an SCLK through an GATE_IP_* register looks a bit unusual. The
> original entry for this clock had SRC_MASK_FSYS register used. Also there is
> the GATE_TOP_SCLK_FSYS register, are you sure that there is no bit for this
> clock there?

Thanks for catching this. SRC_MASK_FSYS is the right offset for this clock.
I will update this in next series.

Regards,
Shaik

>
> Best regards,
> Tomasz
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diff mbox

Patch

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index f0460b4..6d88ae2 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -85,6 +85,7 @@ 
 #define GATE_BUS_TOP		0x10700
 #define GATE_BUS_GEN		0x1073c
 #define GATE_BUS_FSYS0		0x10740
+#define GATE_BUS_FSYS2		0x10748
 #define GATE_BUS_PERIC		0x10750
 #define GATE_BUS_PERIC1		0x10754
 #define GATE_BUS_PERIS0		0x10760
@@ -97,6 +98,7 @@ 
 #define GATE_IP_DISP1		0x10928
 #define GATE_IP_G3D		0x10930
 #define GATE_IP_GEN		0x10934
+#define GATE_IP_FSYS		0x10944
 #define GATE_IP_PERIC		0x10950
 #define GATE_IP_PERIS		0x10960
 #define GATE_IP_MSCL		0x10970
@@ -177,6 +179,7 @@  static unsigned long exynos5420_clk_regs[] __initdata = {
 	GATE_BUS_TOP,
 	GATE_BUS_GEN,
 	GATE_BUS_FSYS0,
+	GATE_BUS_FSYS2,
 	GATE_BUS_PERIC,
 	GATE_BUS_PERIC1,
 	GATE_BUS_PERIS0,
@@ -189,6 +192,7 @@  static unsigned long exynos5420_clk_regs[] __initdata = {
 	GATE_IP_DISP1,
 	GATE_IP_G3D,
 	GATE_IP_GEN,
+	GATE_IP_FSYS,
 	GATE_IP_PERIC,
 	GATE_IP_PERIS,
 	GATE_IP_MSCL,
@@ -269,6 +273,8 @@  PNAME(mout_sw_aclk66_p)	= {"dout_aclk66", "mout_sclk_spll"};
 PNAME(mout_user_aclk66_peric_p)	= { "fin_pll", "mout_sw_aclk66" };
 
 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
+PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
+PNAME(mout_user_pclk200_fsys_p)	= {"fin_pll", "mout_sw_pclk200_fsys"};
 PNAME(mout_user_aclk200_fsys_p)	= {"fin_pll", "mout_sw_aclk200_fsys"};
 
 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
@@ -381,6 +387,7 @@  static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
 	MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
 	MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
 	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
+	MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
 	MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
 
 	MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
@@ -412,6 +419,8 @@  static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
 			SRC_TOP3, 16, 1),
 	MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
 			SRC_TOP3, 20, 1),
+	MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
+			SRC_TOP3, 24, 1),
 	MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
 			SRC_TOP3, 28, 1),
 
@@ -466,6 +475,8 @@  static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
 			SRC_TOP10, 16, 1),
 	MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
 			SRC_TOP10, 20, 1),
+	MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
+			SRC_TOP10, 24, 1),
 	MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
 			SRC_TOP10, 28, 1),
 
@@ -518,6 +529,7 @@  static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
 	MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
 	MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
 	MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
+	MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
 
 	/* PERIC Block */
 	MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
@@ -600,6 +612,7 @@  static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
 	DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
 
 	DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
+	DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
 
 	/* UART and PWM */
 	DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
@@ -736,12 +749,9 @@  static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 	GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
 		GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
-		GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
+		GATE_TOP_SCLK_FSYS, 9, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
-		GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
-
-	GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
-		SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+		GATE_TOP_SCLK_FSYS, 10, CLK_IGNORE_UNUSED, 0),
 
 	/* Display */
 	GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
@@ -760,20 +770,23 @@  static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 		GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
 		GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
-	/* FSYS */
+
+	/* FSYS Block */
 	GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
 	GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
 	GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
 	GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
-	GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
-	GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
-	GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
-	GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
+	GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
+	GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
+	GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
+	GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
 	GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
-			GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
-	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
-	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
-	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
+			GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
+	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
+	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
+	GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
+			GATE_IP_FSYS, 23, CLK_SET_RATE_PARENT, 0),
 
 	/* PERIC Block */
 	GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_IP_PERIC, 0, 0, 0),