From patchwork Tue May 6 16:26:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaik Ameer Basha X-Patchwork-Id: 4122991 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DC5E59F1E1 for ; Tue, 6 May 2014 16:28:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0B47D2024C for ; Tue, 6 May 2014 16:28:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 15F172020F for ; Tue, 6 May 2014 16:28:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751694AbaEFQ22 (ORCPT ); Tue, 6 May 2014 12:28:28 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:17947 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751656AbaEFQ20 (ORCPT ); Tue, 6 May 2014 12:28:26 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N550093RV3DZH60@mailout2.samsung.com>; Wed, 07 May 2014 01:28:25 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.124]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 42.8C.09952.9AD09635; Wed, 07 May 2014 01:28:25 +0900 (KST) X-AuditID: cbfee690-b7fcd6d0000026e0-40-53690da9455f Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 34.E9.25708.9AD09635; Wed, 07 May 2014 01:28:25 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N5500E53V22AU90@mmp2.samsung.com>; Wed, 07 May 2014 01:28:25 +0900 (KST) From: Shaik Ameer Basha To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, tomasz.figa@gmail.com, t.figa@samsung.com, joshi@samsung.com, shaik.samsung@gmail.com, r.sh.open@gmail.com, alim.akhtar@samsung.com, Shaik Ameer Basha , Rahul Sharma Subject: [PATCH v4 13/15] clk: exynos5420: update clocks for MAU Block Date: Tue, 06 May 2014 21:56:48 +0530 Message-id: <1399393610-23394-14-git-send-email-shaik.ameer@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1399393610-23394-1-git-send-email-shaik.ameer@samsung.com> References: <1399393610-23394-1-git-send-email-shaik.ameer@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAIsWRmVeSWpSXmKPExsWyRsSkRnclb2awwYR1shYP5m1js5h/5Byr xfddX9gtehdcZbPY9Pgaq8WM8/uYLJ5OuMhmsfBFvMWURYdZLY483M1usW7nJHaL9TNes1is 2vWH0YHXY+esu+wed67tYfPYvKTeo2/LKkaPz5vkAlijuGxSUnMyy1KL9O0SuDJ6Jv5nKpgo U7GnK7+B8bF4FyMnh4SAicSL2U1sELaYxIV764FsLg4hgaWMEnserGWCKVq6awcTRGI6o8Sm jZ/ZIZwJTBK37/ezg1SxCRhKbL93hbWLkYNDRCBTYuOWXJAaZoHJTBKfHzeA1QgLuEl8W7GU FcRmEVCVuPhqOdgGXgEPia3fv7KA9EoIKEjMmWQDEuYECh96eR2sXEjAXeL0isuMEAedYpfY eMoeYoyAxLfJh6BaZSU2HWCGKJGUOLjiBssERuEFjAyrGEVTC5ILipPSi0z0ihNzi0vz0vWS 83M3MQJj4/S/ZxN2MN47YH2IMRlo3ERmKdHkfGBs5ZXEGxqbGVmYmpgaG5lbmpEmrCTOq/Yo KUhIID2xJDU7NbUgtSi+qDQntfgQIxMHp1QDI/Mvi5cah67H/DB+of/zT1IN96m9b1Zf0Vvm 7bb2zdRvls6RKetdmMOEdHuEDglst/BVveK/2ZDJQvjBK1OuU9bVIWdMTf4zC66xWxttbX3d MCx/dV308hUbWBX3dR1Rsysw27RcPpNrx6lfnolbxB+YiHvzbd3Dxi9Q0RvdfyjmlCh/+5kZ SizFGYmGWsxFxYkAb36K56MCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrHIsWRmVeSWpSXmKPExsVy+t9jQd2VvJnBBku3ilk8mLeNzWL+kXOs Ft93fWG36F1wlc1i0+NrrBYzzu9jsng64SKbxcIX8RZTFh1mtTjycDe7xbqdk9gt1s94zWKx atcfRgdej52z7rJ73Lm2h81j85J6j74tqxg9Pm+SC2CNamC0yUhNTEktUkjNS85PycxLt1Xy Do53jjc1MzDUNbS0MFdSyEvMTbVVcvEJ0HXLzAG6UUmhLDGnFCgUkFhcrKRvh2lCaIibrgVM Y4Sub0gQXI+RARpIWMOY0TPxP1PBRJmKPV35DYyPxbsYOTkkBEwklu7awQRhi0lcuLeerYuR i0NIYDqjxKaNn9khnAlMErfv97ODVLEJGEpsv3eFtYuRg0NEIFNi45ZckBpmgclMEp8fN4DV CAu4SXxbsZQVxGYRUJW4+Go52AZeAQ+Jrd+/soD0SggoSMyZZAMS5gQKH3p5HaxcSMBd4vSK y4wTGHkXMDKsYhRNLUguKE5KzzXSK07MLS7NS9dLzs/dxAiOvWfSOxhXNVgcYhTgYFTi4bV4 mxEsxJpYVlyZe4hRgoNZSYT3DltmsBBvSmJlVWpRfnxRaU5q8SHGZKCjJjJLiSbnA9NCXkm8 obGJuamxqaWJhYmZJWnCSuK8B1utA4UE0hNLUrNTUwtSi2C2MHFwSjUwCgRM+53bWN/QMEt3 vUP/2hbDa9o8rnMlK11WXq7UUQ+y3Wm3Qi42szr89C2Wrctu8prfbnlTOWV5AId6/s4ppnN9 NXMzaza+FXv1guf75tNBaVkdQTUTXG5MbZ/wcM8PFz6vHXq3Yt+lSYX4rncv4Ij1ttGoeNlY lxir1+HTveE8wy6uHAElluKMREMt5qLiRABOG2tiAQMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the missing MAU block specific clocks. Signed-off-by: Rahul Sharma Signed-off-by: Shaik Ameer Basha --- drivers/clk/samsung/clk-exynos5420.c | 14 +++++++++++++- include/dt-bindings/clock/exynos5420.h | 2 ++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index ba7273a..e0e749d 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -62,7 +62,9 @@ #define SRC_TOP11 0x10284 #define SRC_TOP12 0x10288 #define SRC_MASK_TOP2 0x10308 +#define SRC_MASK_TOP7 0x1031c #define SRC_MASK_DISP10 0x1032c +#define SRC_MASK_MAU 0x10334 #define SRC_MASK_FSYS 0x10340 #define SRC_MASK_PERIC0 0x10350 #define SRC_MASK_PERIC1 0x10354 @@ -155,6 +157,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = { SRC_TOP11, SRC_TOP12, SRC_MASK_TOP2, + SRC_MASK_TOP7, SRC_MASK_DISP10, SRC_MASK_FSYS, SRC_MASK_PERIC0, @@ -351,6 +354,8 @@ PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; +PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", + "mout_sclk_mpll", "mout_sclk_spll"}; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { @@ -373,6 +378,9 @@ static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initda static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2), MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2), + MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, + SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), + MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1), @@ -520,7 +528,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { TOP_SPARE2, 8, 1, CLK_SET_RATE_PARENT, 0), /* MAU Block */ - MUX(0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), + MUX_F(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3, + CLK_SET_RATE_PARENT, 0), /* FSYS Block */ MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), @@ -713,6 +722,9 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE(CLK_ACLK300_DISP1, "aclk300_disp1", "mout_user_aclk300_disp1", SRC_MASK_TOP2, 24, CLK_IGNORE_UNUSED, 0), + GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", + SRC_MASK_TOP7, 20, CLK_IGNORE_UNUSED, 0), + /* sclk */ GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index f5459c1..4831267 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -58,6 +58,7 @@ #define CLK_SCLK_GSCL_WA 156 #define CLK_SCLK_GSCL_WB 157 #define CLK_SCLK_HDMIPHY 158 +#define CLK_MAU_EPLL 159 /* gate clocks */ #define CLK_ACLK66_PERIC 256 @@ -197,6 +198,7 @@ #define CLK_MOUT_HDMI 640 #define CLK_MOUT_G3D 641 #define CLK_MOUT_VPLL 642 +#define CLK_MOUT_MAUDIO0 643 /* divider clocks */ #define CLK_DOUT_PIXEL 768