From patchwork Tue May 6 16:26:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaik Ameer Basha X-Patchwork-Id: 4122911 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0C7D9BFF02 for ; Tue, 6 May 2014 16:28:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3C24520253 for ; Tue, 6 May 2014 16:28:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4AC092020F for ; Tue, 6 May 2014 16:28:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751486AbaEFQ2N (ORCPT ); Tue, 6 May 2014 12:28:13 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:32369 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751400AbaEFQ2L (ORCPT ); Tue, 6 May 2014 12:28:11 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N5500NPPV2X5350@mailout4.samsung.com>; Wed, 07 May 2014 01:28:09 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.124]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id B7.B3.11496.99D09635; Wed, 07 May 2014 01:28:09 +0900 (KST) X-AuditID: cbfee691-b7f3e6d000002ce8-d9-53690d9905fe Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 2D.D9.25708.89D09635; Wed, 07 May 2014 01:28:09 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N5500E53V22AU90@mmp2.samsung.com>; Wed, 07 May 2014 01:28:08 +0900 (KST) From: Shaik Ameer Basha To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, tomasz.figa@gmail.com, t.figa@samsung.com, joshi@samsung.com, shaik.samsung@gmail.com, r.sh.open@gmail.com, alim.akhtar@samsung.com, Shaik Ameer Basha , Rahul Sharma Subject: [PATCH v4 05/15] clk: exynos5420: update clocks for G2D and G3D blocks Date: Tue, 06 May 2014 21:56:40 +0530 Message-id: <1399393610-23394-6-git-send-email-shaik.ameer@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1399393610-23394-1-git-send-email-shaik.ameer@samsung.com> References: <1399393610-23394-1-git-send-email-shaik.ameer@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIIsWRmVeSWpSXmKPExsWyRsSkRncmb2awwYyZPBYP5m1js5h/5Byr xfddX9gtehdcZbPY9Pgaq8WM8/uYLJ5OuMhmsfBFvMWURYdZLY483M1usW7nJHaL9TNes1is 2vWH0YHXY+esu+wed67tYfPYvKTeo2/LKkaPz5vkAlijuGxSUnMyy1KL9O0SuDKmNPWwF5wV r/jatZu1gbFRpIuRk0NCwETi0a/vLBC2mMSFe+vZuhi5OIQEljJKnLl1gxGm6P/eKawQiemM Es+PbmOGcCYwSRyfegWsik3AUGL7vStAVRwcIgKZEhu35ILUMAtMZpL4/LiBHaRGWMBf4sLs 1WDrWARUJR783sAGYvMKuEv8PHuYEaRXQkBBYs4kG5Awp4CHxKGX11lBbCGgktMrLkMddI5d ovF1NsQYAYlvkw+xQLTKSmw6wAxRIilxcMUNlgmMwgsYGVYxiqYWJBcUJ6UXmeoVJ+YWl+al 6yXn525iBEbH6X/PJu5gvH/A+hBjMtC4icxSosn5wOjKK4k3NDYzsjA1MTU2Mrc0I01YSZw3 /VFSkJBAemJJanZqakFqUXxRaU5q8SFGJg5OqQZGHofQVPfPOx4L3ArO2uPKtOX84StfTjPN ZL/3wqjAmX1qaMh3caZpUrqz3GZW+vcoalvYMW7JniAvfS66j3Pu4fd53M3y6Wzh269vO71N pmjm08Btpa5pOmlLYr9GfLh54dlTdlv1dwdbzfec0jjqKWBU2Rce38Xooup6S6TXvD5Ce07C LQclluKMREMt5qLiRABeP3sNpAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPIsWRmVeSWpSXmKPExsVy+t9jQd2ZvJnBBifXsFo8mLeNzWL+kXOs Ft93fWG36F1wlc1i0+NrrBYzzu9jsng64SKbxcIX8RZTFh1mtTjycDe7xbqdk9gt1s94zWKx atcfRgdej52z7rJ73Lm2h81j85J6j74tqxg9Pm+SC2CNamC0yUhNTEktUkjNS85PycxLt1Xy Do53jjc1MzDUNbS0MFdSyEvMTbVVcvEJ0HXLzAG6UUmhLDGnFCgUkFhcrKRvh2lCaIibrgVM Y4Sub0gQXI+RARpIWMOYMaWph73grHjF167drA2MjSJdjJwcEgImEv/3TmGFsMUkLtxbz9bF yMUhJDCdUeL50W3MEM4EJonjU68wglSxCRhKbL93BaiDg0NEIFNi45ZckBpmgclMEp8fN7CD 1AgL+EtcmL2aBcRmEVCVePB7AxuIzSvgLvHz7GFGkF4JAQWJOZNsQMKcAh4Sh15eBztCCKjk 9IrLjBMYeRcwMqxiFE0tSC4oTkrPNdIrTswtLs1L10vOz93ECI6+Z9I7GFc1WBxiFOBgVOLh tXibESzEmlhWXJl7iFGCg1lJhPcOW2awEG9KYmVValF+fFFpTmrxIcZkoKMmMkuJJucDE0Ne SbyhsYm5qbGppYmFiZklacJK4rwHW60DhQTSE0tSs1NTC1KLYLYwcXBKNTDmJvZImCY6bWyX yWCSu/S45InYdZmV7S7ypw91Kf+wFNx7YMHd2DrHOQsZri0pvx7vM+n9DvM9q5ackKvrXGwp e/+PQZJecQz3Q+/VzXb2H/0XJvZ/tfe64brn8GX1SynTZ3zbY9A8zcr286X0n7t8JyiWiZcz vk6483Rans75F7e0whbdeN2vxFKckWioxVxUnAgAcET4/QIDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds missing clocks of G2D block. It also removes the aclkg3d alias from G3D block clocks. Signed-off-by: Rahul Sharma Signed-off-by: Shaik Ameer Basha --- drivers/clk/samsung/clk-exynos5420.c | 17 ++++++++++++++--- include/dt-bindings/clock/exynos5420.h | 2 ++ 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 320f72d..5bc4798 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -27,6 +27,7 @@ #define DIV_CPU1 0x504 #define GATE_BUS_CPU 0x700 #define GATE_SCLK_CPU 0x800 +#define GATE_IP_G2D 0x8800 #define CPLL_LOCK 0x10020 #define DPLL_LOCK 0x10030 #define EPLL_LOCK 0x10040 @@ -402,8 +403,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 8, 1), MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, SRC_TOP5, 12, 1), - MUX_A(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, - SRC_TOP5, 16, 1, "aclkg3d"), + MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, + SRC_TOP5, 16, 1), MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, SRC_TOP5, 20, 1), MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p, @@ -830,6 +831,16 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 0), + /* G2D */ + GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", + GATE_IP_G2D, 1, CLK_IGNORE_UNUSED, 0), + GATE(CLK_G2D, "g2d", "aclk333_g2d", + GATE_IP_G2D, 3, CLK_IGNORE_UNUSED, 0), + GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", + GATE_IP_G2D, 5, CLK_IGNORE_UNUSED, 0), + GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", + GATE_IP_G2D, 7, CLK_IGNORE_UNUSED, 0), + /* ISP */ GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), @@ -850,7 +861,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), - GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0), + GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 6e22fdd..bf85418 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -177,6 +177,8 @@ #define CLK_ACLK_G3D 500 #define CLK_G3D 501 #define CLK_SMMU_MIXER 502 +#define CLK_SMMU_G2D 503 +#define CLK_SMMU_MDMA0 504 #define CLK_SCLK_UART_ISP 510 #define CLK_SCLK_SPI0_ISP 511 #define CLK_SCLK_SPI1_ISP 512