From patchwork Thu May 8 10:52:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas Sajjan X-Patchwork-Id: 4135211 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E66E4BFF02 for ; Thu, 8 May 2014 10:53:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D50C320253 for ; Thu, 8 May 2014 10:53:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8BD0320171 for ; Thu, 8 May 2014 10:53:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753534AbaEHKx5 (ORCPT ); Thu, 8 May 2014 06:53:57 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:22940 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753015AbaEHKx4 (ORCPT ); Thu, 8 May 2014 06:53:56 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N5900LPO4XU7T40@mailout3.samsung.com> for linux-samsung-soc@vger.kernel.org; Thu, 08 May 2014 19:53:54 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.125]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 38.B6.09952.2426B635; Thu, 08 May 2014 19:53:54 +0900 (KST) X-AuditID: cbfee690-b7fcd6d0000026e0-11-536b62420dbc Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 79.86.25708.2426B635; Thu, 08 May 2014 19:53:54 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N5900G214XK4O90@mmp1.samsung.com>; Thu, 08 May 2014 19:53:54 +0900 (KST) From: Vikas Sajjan To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, pankaj.dubey@samsung.com, Vikas Sajjan , Abhilash Kesavan Subject: [PATCH V3 2/3] ARM: EXYNOS5: Add Suspend-to-RAM support for 5420 Date: Thu, 08 May 2014 16:22:48 +0530 Message-id: <1399546368-30537-1-git-send-email-vikas.sajjan@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrNLMWRmVeSWpSXmKPExsWyRsSkVtcpKTvY4PZpU4vHaxYzWXzf9YXd onfBVTaLTY+vsVrMOL+PyWLRVqDYql1/GC1uPtvO5MDhsXPWXXaPzUvqPfq2rGL0+LxJLoAl issmJTUnsyy1SN8ugStj9ebnjAWnAyumz/vN2sB43aWLkZNDQsBEYu/Ov8wQtpjEhXvr2boY uTiEBJYySnQ0nWCEKVr8+iCYLSSwiFHi+s8siKIJTBInuxYwgSTYBHQlVpx6DtTNwSEi4C2x /JoiSA2zwBZGiUkr7rCD1AgLeErMntkONohFQFVi/dPpjCD1vAIeEs82BIGYEgIKEnMm2YC0 Sgg0s0u0bZ3PClEuIPFt8iEWiBpZiU0HoG6WlDi44gbLBEbBBYwMqxhFUwuSC4qT0otM9IoT c4tL89L1kvNzNzECA/b0v2cTdjDeO2B9iDEZaNxEZinR5HxgwOeVxBsamxlZmJqYGhuZW5qR Jqwkzqv2KClISCA9sSQ1OzW1ILUovqg0J7X4ECMTB6dUA2O/2/Yl/mGTlx5Ijj2/oSQ2x87c 7pe0W9sKZ583pzaw79idXafTJbvnmICWPNOPMgb2JUtM0+QMzru0duS3HVSpuPpC+fikkszq zr+O/8LuqziKLRdPDDL6EZEqXOTKk+Ms06L1YPo57kUbP4vETVr+48fxosr43nSec6z3SzS5 rL+c5T1wUImlOCPRUIu5qDgRAD+GsC5uAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrBIsWRmVeSWpSXmKPExsVy+t9jAV2npOxgg1OntS0er1nMZPF91xd2 i94FV9ksNj2+xmox4/w+JotFW4Fiq3b9YbS4+Ww7kwOHx85Zd9k9Ni+p9+jbsorR4/MmuQCW qAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zBygM5QU yhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGas3P2csOB1YMX3eb9YGxusu XYycHBICJhKLXx9khLDFJC7cW88GYgsJLGKUuP4zq4uRC8iewCRxsmsBE0iCTUBXYsWp50BF HBwiAt4Sy68pgtQwC2xhlJi04g47SI2wgKfE7JntYENZBFQl1j+dzghSzyvgIfFsQxCIKSGg IDFnks0ERu4FjAyrGEVTC5ILipPSc430ihNzi0vz0vWS83M3MYLj4Zn0DsZVDRaHGAU4GJV4 eDOcs4KFWBPLiitzDzFKcDArifDy+GcHC/GmJFZWpRblxxeV5qQWH2JMBto9kVlKNDkfGKt5 JfGGxibmpsamliYWJmaWpAkrifMebLUOFBJITyxJzU5NLUgtgtnCxMEp1cA40bpPuURF65z3 YeG/IRPsfp13iM6LehrCK7/9W7l9/0SxtOA90WF7b5W52/+s/XlAxnhV9hvhxiazdbtkHwo/ XpZmZXnMxHzKmUXtf34KFPPueaTKk/7YrUfTuKuKazGrKKto5fHISAUNV8uZ/V5RC0QDNvCu 6OVmmt51aOqbg57a3BNb7yqxFGckGmoxFxUnAgDAUP4dywIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds Suspend-to-RAM support for EXYNOS5420 Signed-off-by: Abhilash Kesavan Signed-off-by: Vikas Sajjan --- arch/arm/mach-exynos/pm.c | 163 ++++++++++++++++++++++++++++++++++----- arch/arm/mach-exynos/regs-pmu.h | 2 + 2 files changed, 146 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index a7a1b7f..87ccac7 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -40,6 +40,9 @@ #include "regs-sys.h" #include "exynos-pmu.h" +#define EXYNOS5420_VA_CPU_STATE (S5P_VA_SYSRAM + 0x28) +#define EXYNOS5420_VA_CPU_ADDR (S5P_VA_SYSRAM_NS + 0x1C) + static struct regmap *pmu_regmap; /** @@ -65,6 +68,19 @@ static struct sleep_save exynos_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), }; +static struct sleep_save exynos5420_cpustate_save[] = { + SAVE_ITEM(EXYNOS5420_VA_CPU_STATE), + SAVE_ITEM(EXYNOS5420_VA_CPU_ADDR), +}; + +static struct sleep_save exynos5420_pmu_reg_save[] = { + SAVE_ITEM(S5P_PMU_SPARE3), +}; + +static struct sleep_save exynos5420_reg_save[] = { + SAVE_ITEM(EXYNOS5_SYS_DISP1_BLK_CFG), +}; + /* * GIC wake-up support */ @@ -87,7 +103,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) { const struct exynos_wkup_irq *wkup_irq; - if (soc_is_exynos5250()) + if (soc_is_exynos5250() || soc_is_exynos5420()) wkup_irq = exynos5250_wkup_irq; else wkup_irq = exynos4_wkup_irq; @@ -188,7 +204,15 @@ static int exynos_cpu_suspend(unsigned long arg) outer_flush_all(); #endif - if (soc_is_exynos5250()) + /* + * Clear IRAM register for cpu state so that primary CPU does + * not enter low power start in U-Boot. + * This is specific to exynos5420 SoC only. + */ + if (soc_is_exynos5420()) + __raw_writel(0x0, EXYNOS5420_VA_CPU_STATE); + + if (soc_is_exynos5250() || soc_is_exynos5420()) flush_cache_all(); /* issue the standby signal into the pm unit. */ @@ -216,6 +240,26 @@ static void exynos_pm_prepare(void) regmap_read(pmu_regmap, EXYNOS5_JPEG_MEM_OPTION, &tmp); tmp &= ~EXYNOS5_OPTION_USE_RETENTION; regmap_write(pmu_regmap, EXYNOS5_JPEG_MEM_OPTION, tmp); + } else if (soc_is_exynos5420()) { + + unsigned i; + + s3c_pm_do_save(exynos5420_reg_save, + ARRAY_SIZE(exynos5420_reg_save)); + + for (i = 0; i < ARRAY_SIZE(exynos5420_pmu_reg_save); i++) + regmap_read(pmu_regmap, + (unsigned int)exynos5420_pmu_reg_save[i].reg, + (unsigned int *)&exynos5420_pmu_reg_save[i].val); + /* + * The cpu state needs to be saved and restored so that the + * secondary CPUs will enter low power start. Though the U-Boot + * is setting the cpu state with low power flag, the kernel + * needs to restore it back in case, the primary cpu fails to + * suspend for any reason + */ + s3c_pm_do_save(exynos5420_cpustate_save, + ARRAY_SIZE(exynos5420_cpustate_save)); } /* Set value of power down register for sleep mode */ @@ -226,6 +270,26 @@ static void exynos_pm_prepare(void) /* ensure at least INFORM0 has the resume address */ regmap_write(pmu_regmap, S5P_INFORM0, virt_to_phys(exynos_cpu_resume)); + + if (soc_is_exynos5420()) { + regmap_read(pmu_regmap, EXYNOS5_ARM_L2_OPTION, &tmp); + tmp &= ~EXYNOS5_USE_RETENTION; + regmap_write(pmu_regmap, EXYNOS5_ARM_L2_OPTION, tmp); + + regmap_read(pmu_regmap, EXYNOS5420_SFR_AXI_CGDIS1, &tmp); + tmp |= EXYNOS5420_UFS; + regmap_write(pmu_regmap, EXYNOS5420_SFR_AXI_CGDIS1, tmp); + + regmap_read(pmu_regmap, EXYNOS5420_ARM_COMMON_OPTION, &tmp); + tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE; + regmap_write(pmu_regmap, EXYNOS5420_ARM_COMMON_OPTION, tmp); + regmap_read(pmu_regmap, EXYNOS5420_FSYS2_OPTION, &tmp); + tmp |= EXYNOS5420_EMULATION; + regmap_write(pmu_regmap, EXYNOS5420_FSYS2_OPTION, tmp); + regmap_read(pmu_regmap, EXYNOS5420_PSGEN_OPTION, &tmp); + tmp |= EXYNOS5420_EMULATION; + regmap_write(pmu_regmap, EXYNOS5420_PSGEN_OPTION, tmp); + } } static void exynos_pm_central_suspend(void) @@ -242,12 +306,20 @@ static int exynos_pm_suspend(void) { unsigned int tmp; + unsigned int this_cluster; exynos_pm_central_suspend(); /* Setting SEQ_OPTION register */ - - tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); - regmap_write(pmu_regmap, S5P_CENTRAL_SEQ_OPTION, tmp); + if (soc_is_exynos5420()) { + this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); + if (!this_cluster) + regmap_write(pmu_regmap, S5P_CENTRAL_SEQ_OPTION, EXYNOS5420_ARM_USE_STANDBY_WFI0); + else + regmap_write(pmu_regmap, S5P_CENTRAL_SEQ_OPTION, EXYNOS5420_KFC_USE_STANDBY_WFI0); + } else { + tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); + regmap_write(pmu_regmap, S5P_CENTRAL_SEQ_OPTION, tmp); + } if (!soc_is_exynos5250()) exynos_cpu_save_register(); @@ -280,33 +352,80 @@ static int exynos_pm_central_resume(void) static void exynos_pm_resume(void) { + unsigned int tmp; + if (soc_is_exynos5420()) { + /* Restore the IRAM register cpu state */ + s3c_pm_do_restore(exynos5420_cpustate_save, + ARRAY_SIZE(exynos5420_cpustate_save)); + + regmap_write(pmu_regmap, S5P_CENTRAL_SEQ_OPTION, + EXYNOS5420_USE_STANDBY_WFI_ALL); + } + if (exynos_pm_central_resume()) goto early_wakeup; - if (!soc_is_exynos5250()) + if (!(soc_is_exynos5250() || soc_is_exynos5420())) exynos_cpu_restore_register(); /* For release retention */ - regmap_write(pmu_regmap, S5P_PAD_RET_MAUDIO_OPTION, (1 << 28)); - regmap_write(pmu_regmap, S5P_PAD_RET_GPIO_OPTION, (1 << 28)); - regmap_write(pmu_regmap, S5P_PAD_RET_UART_OPTION, (1 << 28)); - regmap_write(pmu_regmap, S5P_PAD_RET_MMCA_OPTION, (1 << 28)); - regmap_write(pmu_regmap, S5P_PAD_RET_MMCB_OPTION, (1 << 28)); - regmap_write(pmu_regmap, S5P_PAD_RET_EBIA_OPTION, (1 << 28)); - regmap_write(pmu_regmap, S5P_PAD_RET_EBIB_OPTION, (1 << 28)); + if (soc_is_exynos5250()) { + regmap_write(pmu_regmap, S5P_PAD_RET_MAUDIO_OPTION, (1 << 28)); + regmap_write(pmu_regmap, S5P_PAD_RET_GPIO_OPTION, (1 << 28)); + regmap_write(pmu_regmap, S5P_PAD_RET_UART_OPTION, (1 << 28)); + regmap_write(pmu_regmap, S5P_PAD_RET_MMCA_OPTION, (1 << 28)); + regmap_write(pmu_regmap, S5P_PAD_RET_MMCB_OPTION, (1 << 28)); + regmap_write(pmu_regmap, S5P_PAD_RET_EBIA_OPTION, (1 << 28)); + regmap_write(pmu_regmap, S5P_PAD_RET_EBIB_OPTION, (1 << 28)); + } else if (soc_is_exynos5420()) { + regmap_write(pmu_regmap, EXYNOS_PAD_RET_DRAM_OPTION, (1 << 28)); + regmap_write(pmu_regmap, EXYNOS_PAD_RET_MAUDIO_OPTION, (1 << 28)); + regmap_write(pmu_regmap, EXYNOS_PAD_RET_JTAG_OPTION, (1 << 28)); + regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_GPIO_OPTION, (1 << 28)); + regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_UART_OPTION, (1 << 28)); + regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_MMCA_OPTION, (1 << 28)); + regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_MMCB_OPTION, (1 << 28)); + regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_MMCC_OPTION, (1 << 28)); + regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_HSI_OPTION, (1 << 28)); + regmap_write(pmu_regmap, EXYNOS_PAD_RET_EBIA_OPTION, (1 << 28)); + regmap_write(pmu_regmap, EXYNOS_PAD_RET_EBIB_OPTION, (1 << 28)); + regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_SPI_OPTION, (1 << 28)); + regmap_write(pmu_regmap, EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, (1 << 28)); + } - if (soc_is_exynos5250()) + if (soc_is_exynos5250()) { s3c_pm_do_restore(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); + } else if (soc_is_exynos5420()) { + unsigned int i; + s3c_pm_do_restore(exynos5420_reg_save, + ARRAY_SIZE(exynos5420_reg_save)); + for (i = 0; i < ARRAY_SIZE(exynos5420_pmu_reg_save); i++) + regmap_write(pmu_regmap, + (unsigned int)exynos5420_pmu_reg_save[i].reg, + (unsigned int)exynos5420_pmu_reg_save[i].val); + } s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); - if (!soc_is_exynos5250()) + if (!soc_is_exynos5250() && !soc_is_exynos5420()) scu_enable(S5P_VA_SCU); early_wakeup: + if (soc_is_exynos5420()) { + regmap_read(pmu_regmap, EXYNOS5420_SFR_AXI_CGDIS1, &tmp); + tmp &= ~EXYNOS5420_UFS; + regmap_write(pmu_regmap, EXYNOS5420_SFR_AXI_CGDIS1, tmp); + regmap_read(pmu_regmap, EXYNOS5420_FSYS2_OPTION, &tmp); + tmp &= ~EXYNOS5420_EMULATION; + regmap_write(pmu_regmap, EXYNOS5420_FSYS2_OPTION, tmp); + regmap_read(pmu_regmap, EXYNOS5420_PSGEN_OPTION, &tmp); + tmp &= ~EXYNOS5420_EMULATION; + regmap_write(pmu_regmap, EXYNOS5420_PSGEN_OPTION, tmp); + } + /* Clear SLEEP mode set in INFORM1 */ regmap_write(pmu_regmap, S5P_INFORM1, 0x0); @@ -395,7 +514,7 @@ static int exynos_cpu_pm_notifier(struct notifier_block *self, case CPU_PM_EXIT: if (cpu == 0) { - if (!soc_is_exynos5250()) + if (!(soc_is_exynos5250() || soc_is_exynos5420())) scu_enable(S5P_VA_SCU); exynos_cpu_restore_register(); exynos_pm_central_resume(); @@ -421,9 +540,15 @@ void __init exynos_pm_init(void) gic_arch_extn.irq_set_wake = exynos_irq_set_wake; /* All wakeup disable */ - regmap_read(pmu_regmap, S5P_WAKEUP_MASK, &tmp); - tmp |= ((0xFF << 8) | (0x1F << 1)); - regmap_write(pmu_regmap, S5P_WAKEUP_MASK, tmp); + if (soc_is_exynos5420()) { + regmap_read(pmu_regmap, S5P_WAKEUP_MASK, &tmp); + tmp |= ((0x7F << 7) | (0x1F << 1)); + regmap_write(pmu_regmap, S5P_WAKEUP_MASK, tmp); + } else { + regmap_read(pmu_regmap, S5P_WAKEUP_MASK, &tmp); + tmp |= ((0xFF << 8) | (0x1F << 1)); + regmap_write(pmu_regmap, S5P_WAKEUP_MASK, tmp); + } register_syscore_ops(&exynos_pm_syscore_ops); suspend_set_ops(&exynos_suspend_ops); diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 39a8300..955ee07 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -35,6 +35,7 @@ #define S5P_INFORM5 (0x0814) #define S5P_INFORM6 (0x0818) #define S5P_INFORM7 (0x081C) +#define S5P_PMU_SPARE3 (0x090c) #define EXYNOS_IROM_DATA2 (0x0988) #define S5P_ARM_CORE0_LOWPWR (0x1000) @@ -211,6 +212,7 @@ /* For EXYNOS5 */ +#define EXYNOS5_SYS_DISP1_BLK_CFG S5P_SYSREG(0x0214) #define EXYNOS5_AUTO_WDTRESET_DISABLE (0x0408) #define EXYNOS5_MASK_WDTRESET_REQUEST (0x040C)