From patchwork Thu May 8 11:27:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaik Ameer Basha X-Patchwork-Id: 4135461 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3DC1DBFF02 for ; Thu, 8 May 2014 11:30:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 52F45201ED for ; Thu, 8 May 2014 11:30:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3C56D201DC for ; Thu, 8 May 2014 11:30:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753499AbaEHLaY (ORCPT ); Thu, 8 May 2014 07:30:24 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:34682 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753261AbaEHLaX (ORCPT ); Thu, 8 May 2014 07:30:23 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N5900IMD6MMJ990@mailout4.samsung.com>; Thu, 08 May 2014 20:30:22 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.125]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id F4.82.14563.ECA6B635; Thu, 08 May 2014 20:30:22 +0900 (KST) X-AuditID: cbfee68e-b7fd86d0000038e3-6e-536b6aceae10 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 3D.4E.25708.ECA6B635; Thu, 08 May 2014 20:30:22 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N59000DR6K7QQ00@mmp1.samsung.com>; Thu, 08 May 2014 20:30:22 +0900 (KST) From: Shaik Ameer Basha To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, t.figa@samsung.com, kgene.kim@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, shaik.samsung@gmail.com, r.sh.open@gmail.com, alim.akhtar@samsung.com, Shaik Ameer Basha , Rahul Sharma Subject: [PATCH v5 10/15] clk: exynos5420: update clocks for FSYS and FSYS2 blocks Date: Thu, 08 May 2014 16:57:59 +0530 Message-id: <1399548484-20626-11-git-send-email-shaik.ameer@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1399548484-20626-1-git-send-email-shaik.ameer@samsung.com> References: <1399548484-20626-1-git-send-email-shaik.ameer@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAIsWRmVeSWpSXmKPExsWyRsSkVvdcVnawwcIVmhYP5m1js5h/5Byr xfddX9gtehdcZbPY9Pgaq8WM8/uYLJ5OuMhmsfBFvMWURYdZLY483M1usW7nJHaL9TNes1is 2vWH0YHXY+esu+wed67tYfPYvKTeo2/LKkaPz5vkAlijuGxSUnMyy1KL9O0SuDJ6GsoKthpW 3NpwhqWBsUGri5GTQ0LAROLDhruMELaYxIV769m6GLk4hASWMkpM3jGZCabo/Mm7zBCJRYwS 7xZtZYFwJjBJfN26HaydTcBQYvu9K6xdjBwcIgKZEhu35ILUMAtMZpKYu2wuK0iNsECIxLQz n8GmsgioSnztOMEMUs8r4CFxda8LiCkhoCAxZ5INSAUnUHTyr21gnUIC7hJ9/48xgYyUEDjF LtExtYMVYoyAxLfJh1ggemUlNh1ghrhZUuLgihssExiFFzAyrGIUTS1ILihOSi8y0itOzC0u zUvXS87P3cQIjI3T/5717WC8ecD6EGMy0LiJzFKiyfnA2MoriTc0NjOyMDUxNTYytzQjTVhJ nHfRw6QgIYH0xJLU7NTUgtSi+KLSnNTiQ4xMHJxSDYw6uSUB89M3Lj+foGzx5I6BzGSRGVy7 7jhtK+1t/7T27fI2fv/9clHpOTJLVzyRTOrrY9+SlT/3sXnXIkuZulviSxOPun3avIblooRO 7Qsl+3d/p7Zl3A0IkVmg/OqU5bKZydXTFnNUSFYU9+5lqz94+pnhm7A9b34LbOR+8bvy0HLd 6498hFcrsRRnJBpqMRcVJwIA2zG7TKMCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrLIsWRmVeSWpSXmKPExsVy+t9jAd1zWdnBBltnyls8mLeNzWL+kXOs Ft93fWG36F1wlc1i0+NrrBYzzu9jsng64SKbxcIX8RZTFh1mtTjycDe7xbqdk9gt1s94zWKx atcfRgdej52z7rJ73Lm2h81j85J6j74tqxg9Pm+SC2CNamC0yUhNTEktUkjNS85PycxLt1Xy Do53jjc1MzDUNbS0MFdSyEvMTbVVcvEJ0HXLzAG6UUmhLDGnFCgUkFhcrKRvh2lCaIibrgVM Y4Sub0gQXI+RARpIWMOY0dNQVrDVsOLWhjMsDYwNWl2MnBwSAiYS50/eZYawxSQu3FvP1sXI xSEksIhR4t2irSwQzgQmia9btzOCVLEJGEpsv3eFtYuRg0NEIFNi45ZckBpmgclMEnOXzWUF qREWCJGYduYzE4jNIqAq8bXjBDNIPa+Ah8TVvS4gpoSAgsScSTYgFZxA0cm/toF1Cgm4S/T9 P8Y0gZF3ASPDKkbR1ILkguKk9FwjveLE3OLSvHS95PzcTYzgyHsmvYNxVYPFIUYBDkYlHt4M 56xgIdbEsuLK3EOMEhzMSiK8U9Oyg4V4UxIrq1KL8uOLSnNSiw8xJgPdNJFZSjQ5H5gU8kri DY1NzE2NTS1NLEzMLEkTVhLnPdhqHSgkkJ5YkpqdmlqQWgSzhYmDU6qBcbHsL5d1TEv9xL3v fdiSJPf9S6Uid+qCbWGFp9dvvi6cFKArIrgvMHqlwP+WuD3awY6GhfwW7+7ILr1nP2t39mR9 I6cbf9dtmZ64WvmNRtzZ5/YuDIx/ij62ezLu/aK/2H6dhOz1lLmLAq4cD5RmMlv3+/RXoRXC X/p6Fyroll8Q5nGev7AjS4mlOCPRUIu5qDgRADKTBAYAAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds more clocks from FSYS and FSYS2 blocks and uses GATE_IP_* registers for gating IPs. Signed-off-by: Rahul Sharma Signed-off-by: Shaik Ameer Basha --- drivers/clk/samsung/clk-exynos5420.c | 37 +++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index d37592d..9e04677 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -85,6 +85,7 @@ #define GATE_BUS_TOP 0x10700 #define GATE_BUS_GEN 0x1073c #define GATE_BUS_FSYS0 0x10740 +#define GATE_BUS_FSYS2 0x10748 #define GATE_BUS_PERIC 0x10750 #define GATE_BUS_PERIC1 0x10754 #define GATE_BUS_PERIS0 0x10760 @@ -97,6 +98,7 @@ #define GATE_IP_DISP1 0x10928 #define GATE_IP_G3D 0x10930 #define GATE_IP_GEN 0x10934 +#define GATE_IP_FSYS 0x10944 #define GATE_IP_PERIC 0x10950 #define GATE_IP_PERIS 0x10960 #define GATE_IP_MSCL 0x10970 @@ -177,6 +179,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = { GATE_BUS_TOP, GATE_BUS_GEN, GATE_BUS_FSYS0, + GATE_BUS_FSYS2, GATE_BUS_PERIC, GATE_BUS_PERIC1, GATE_BUS_PERIS0, @@ -189,6 +192,7 @@ static unsigned long exynos5420_clk_regs[] __initdata = { GATE_IP_DISP1, GATE_IP_G3D, GATE_IP_GEN, + GATE_IP_FSYS, GATE_IP_PERIC, GATE_IP_PERIS, GATE_IP_MSCL, @@ -269,6 +273,8 @@ PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" }; PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; +PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; +PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; @@ -381,6 +387,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), + MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), @@ -412,6 +419,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { SRC_TOP3, 16, 1), MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, SRC_TOP3, 20, 1), + MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, + SRC_TOP3, 24, 1), MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, SRC_TOP3, 28, 1), @@ -466,6 +475,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { SRC_TOP10, 16, 1), MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, SRC_TOP10, 20, 1), + MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, + SRC_TOP10, 24, 1), MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, SRC_TOP10, 28, 1), @@ -516,6 +527,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), + MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), /* PERIC Block */ MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), @@ -598,6 +610,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = { DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), + DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), /* UART and PWM */ DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), @@ -738,9 +751,6 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), - GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro", - SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), - /* Display */ GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), @@ -758,20 +768,23 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), - /* FSYS */ + + /* FSYS Block */ GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), - GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), - GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), - GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), - GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), + GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), + GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), + GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), + GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), GATE(CLK_SROMC, "sromc", "aclk200_fsys2", - GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), - GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), - GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), - GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), + GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), + GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), + GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), + GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), + GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", + SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), /* PERIC Block */ GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_IP_PERIC, 0, 0, 0),