From patchwork Thu May 8 11:27:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaik Ameer Basha X-Patchwork-Id: 4135401 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D9134BFF02 for ; Thu, 8 May 2014 11:29:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 08780201ED for ; Thu, 8 May 2014 11:29:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 280CF201DC for ; Thu, 8 May 2014 11:29:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753689AbaEHL3i (ORCPT ); Thu, 8 May 2014 07:29:38 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:34568 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753328AbaEHL3h (ORCPT ); Thu, 8 May 2014 07:29:37 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N5900I556LCZ790@mailout4.samsung.com>; Thu, 08 May 2014 20:29:36 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.122]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id D0.23.09952.0AA6B635; Thu, 08 May 2014 20:29:36 +0900 (KST) X-AuditID: cbfee690-b7fcd6d0000026e0-dc-536b6aa0f8f2 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 9E.2E.25708.0AA6B635; Thu, 08 May 2014 20:29:36 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N59000DR6K7QQ00@mmp1.samsung.com>; Thu, 08 May 2014 20:29:36 +0900 (KST) From: Shaik Ameer Basha To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, t.figa@samsung.com, kgene.kim@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, shaik.samsung@gmail.com, r.sh.open@gmail.com, alim.akhtar@samsung.com, Shaik Ameer Basha , Rahul Sharma Subject: [PATCH v5 04/15] clk: exynos5420: fix parent clocks for mscl sysmmu Date: Thu, 08 May 2014 16:57:53 +0530 Message-id: <1399548484-20626-5-git-send-email-shaik.ameer@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1399548484-20626-1-git-send-email-shaik.ameer@samsung.com> References: <1399548484-20626-1-git-send-email-shaik.ameer@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAIsWRmVeSWpSXmKPExsWyRsSkSndBVnawwfkzuhYP5m1js5h/5Byr xfddX9gtehdcZbPY9Pgaq8WM8/uYLJ5OuMhmsfBFvMWURYdZLY483M1usW7nJHaL9TNes1is 2vWH0YHXY+esu+wed67tYfPYvKTeo2/LKkaPz5vkAlijuGxSUnMyy1KL9O0SuDIm/5rKWHCU t+Ld39AGxpPcXYycHBICJhJXvk5ggrDFJC7cW8/WxcjFISSwlFGi4/wboAQHWNGPL/kQ8UWM En+6b7FDOBOYJGa3PWMD6WYTMJTYfu8KK0iDiECmxMYtuSA1zAKTmSTmLpvLClIjLOAjMW3h NzCbRUBVYuGij4wgNq+Au8TFtjWMEMsUJOZMsgEJcwp4SEz+tQ2sXAiopO//MSaQmRICp9gl Tl2eyQYxR0Di2+RDLBC9shKbDjBDPCMpcXDFDZYJjMILGBlWMYqmFiQXFCelF5noFSfmFpfm pesl5+duYgTGxul/zybsYLx3wPoQYzLQuInMUqLJ+cDYyiuJNzQ2M7IwNTE1NjK3NCNNWEmc V+1RUpCQQHpiSWp2ampBalF8UWlOavEhRiYOTqkGRjfVql+ue8XCVk2wuLWhnvfCCcfjK0V6 +ZnO2OjuXekpnzXvkatHzvZzX/+u/PsgZ9L7/xw7Fe/fqw37rr4o7sX7c0eXHWZzOrr4S9Ti 8PeXbz5cv7J70ga2mBLplOXxk022T9om1cx0V35f/5fNnwzCpr/7FxIx5aRn16Wzdio/m3Ze MzjLvvqJEktxRqKhFnNRcSIAeVqLrqMCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrLIsWRmVeSWpSXmKPExsVy+t9jAd0FWdnBBq+uqFg8mLeNzWL+kXOs Ft93fWG36F1wlc1i0+NrrBYzzu9jsng64SKbxcIX8RZTFh1mtTjycDe7xbqdk9gt1s94zWKx atcfRgdej52z7rJ73Lm2h81j85J6j74tqxg9Pm+SC2CNamC0yUhNTEktUkjNS85PycxLt1Xy Do53jjc1MzDUNbS0MFdSyEvMTbVVcvEJ0HXLzAG6UUmhLDGnFCgUkFhcrKRvh2lCaIibrgVM Y4Sub0gQXI+RARpIWMOYMfnXVMaCo7wV7/6GNjCe5O5i5OCQEDCR+PElv4uRE8gUk7hwbz1b FyMXh5DAIkaJP9232CGcCUwSs9uesYFUsQkYSmy/d4UVpFlEIFNi45ZckBpmgclMEnOXzWUF qREW8JGYtvAbmM0ioCqxcNFHRhCbV8Bd4mLbGkaIxQoScybZgIQ5BTwkJv/aBlYuBFTS9/8Y 0wRG3gWMDKsYRVMLkguKk9JzjfSKE3OLS/PS9ZLzczcxgiPvmfQOxlUNFocYBTgYlXh4M5yz goVYE8uKK3MPMUpwMCuJ8E5Nyw4W4k1JrKxKLcqPLyrNSS0+xJgMdNREZinR5HxgUsgriTc0 NjE3NTa1NLEwMbMkTVhJnPdgq3WgkEB6YklqdmpqQWoRzBYmDk6pBsayH3/3fd5wgLct9sWP tYWS5zLPMJ/s+D7DdaIMo9npzNmmk46c8pHdXXnWN/zG2+0HFTMmWH9hU1RdVHZkcv2y3AaG hJCfTgtPMm/9EmPU0qt1TqxLckn9kulzGp57H//JynLdbv09R451+xgKSl4eDfSby1Cyf/15 sTkLG6aLBJiyH1kavNBaiaU4I9FQi7moOBEAMago2AADAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch fixes the parent clocks for mscl sysmmu. Signed-off-by: Rahul Sharma Signed-off-by: Shaik Ameer Basha --- drivers/clk/samsung/clk-exynos5420.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 68e98d4..de4431b 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -582,6 +582,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = { DIV2_RATIO0, 4, 2), DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), + /* MSCL Block */ + DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), + /* ISP Block */ DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), @@ -812,11 +815,11 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), - GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", + GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", GATE_IP_MSCL, 8, 0, 0), - GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", + GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", GATE_IP_MSCL, 9, 0, 0), - GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", + GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", GATE_IP_MSCL, 10, 0, 0), GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),