From patchwork Fri May 9 12:25:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun Kumar K X-Patchwork-Id: 4142661 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D8E059F387 for ; Fri, 9 May 2014 12:25:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DED28201FA for ; Fri, 9 May 2014 12:25:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DAAEF201BB for ; Fri, 9 May 2014 12:25:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751674AbaEIMZZ (ORCPT ); Fri, 9 May 2014 08:25:25 -0400 Received: from mail-pa0-f44.google.com ([209.85.220.44]:35760 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751076AbaEIMZY (ORCPT ); Fri, 9 May 2014 08:25:24 -0400 Received: by mail-pa0-f44.google.com with SMTP id ld10so4314606pab.31 for ; Fri, 09 May 2014 05:25:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=gFxW0zduXgYKtaY7JMiZZmSXIwv6aAhAg5FCFNC0fZQ=; b=B1UC1RK7fPvjXJxIwMzLtiYE357rSQTcap0GG1+Dntyop7swRzo6M7z2rZuHd3tfqn oWVKnCS7gZnImGN7jgzUBLxC7w8uX+LXwDzOEVc5v6oLWZV9rEpi+qzPVibr2+GdfsO8 TC8G7eyOJuqRj4KXjMPt63Dop7HrD005l5/K9oqYYIPLq4lquQ5A4Si0wbY1TsYy4eQw WcplmH1YKgNFO8bbDxx8xIJ79VhcjAmterWq3ItUZz7wLI1db1yHi2eDHnw7LnSXG9/t j/iS3ltoF5zdYDi6pBNaIGfSZa5b12ghAhSXfsw16ZOO+lCcG+GZIRqZfwL60Podf4HG 9tqg== X-Received: by 10.66.188.5 with SMTP id fw5mr9469862pac.63.1399638323606; Fri, 09 May 2014 05:25:23 -0700 (PDT) Received: from localhost.localdomain ([14.140.216.146]) by mx.google.com with ESMTPSA id pq3sm7360780pbb.57.2014.05.09.05.25.20 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 09 May 2014 05:25:23 -0700 (PDT) From: Arun Kumar K To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: kgene.kim@samsung.com, dianders@chromium.org, alim.akhtar@samsung.com, tomasz.figa@gmail.com, olof@lixom.net, arunkk.samsung@gmail.com Subject: [PATCH v2 3/3] ARM: dts: Add peach-pi board support Date: Fri, 9 May 2014 17:55:03 +0530 Message-Id: <1399638303-32600-4-git-send-email-arun.kk@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1399638303-32600-1-git-send-email-arun.kk@samsung.com> References: <1399638303-32600-1-git-send-email-arun.kk@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds support for google peach-pi board having the Exynos5800 SoC. Signed-off-by: Arun Kumar K Signed-off-by: Doug Anderson Reviewed-by: Tomasz Figa --- Changes from v1 - Updated memory node with a safe size of 2GB --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/exynos5800-peach-pi.dts | 144 +++++++++++++++++++++++++++++ 2 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/exynos5800-peach-pi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a934648..cd399a2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -77,7 +77,8 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5420-peach-pit.dtb \ exynos5420-smdk5420.dtb \ exynos5440-sd5v1.dtb \ - exynos5440-ssdk5440.dtb + exynos5440-ssdk5440.dtb \ + exynos5800-peach-pi.dtb dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ecx-2000.dtb diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts new file mode 100644 index 0000000..4ed9ccc --- /dev/null +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -0,0 +1,144 @@ +/* + * Google Peach Pi Rev 10+ board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include +#include +#include "exynos5800.dtsi" + +/ { + model = "Google Peach Pi Rev 10+"; + + compatible = "google,pi-rev16", + "google,pi-rev15", "google,pi-rev14", + "google,pi-rev13", "google,pi-rev12", + "google,pi-rev11", "google,pi-rev10", + "google,pi", "google,peach", "samsung,exynos5800", + "samsung,exynos5"; + + memory { + reg = <0x20000000 0x80000000>; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&power_key_irq>; + + power { + label = "Power"; + gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 1000000 0>; + brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; + default-brightness-level = <7>; + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + }; +}; + +&pinctrl_0 { + tpm_irq: tpm-irq { + samsung,pins = "gpx1-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + power_key_irq: power-key-irq { + samsung,pins = "gpx1-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&rtc { + status = "okay"; +}; + +&uart_3 { + status = "okay"; +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + broken-cd; + caps2-mmc-hs200-1_8v; + supports-highspeed; + non-removable; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +&mmc_2 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&hsi2c_9 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + /* Unused irq; but still need to configure the pins */ + pinctrl-names = "default"; + pinctrl-0 = <&tpm_irq>; + }; +}; + +/* + * Use longest HW watchdog in SoC (32 seconds) since the hardware + * watchdog provides no debugging information (compared to soft/hard + * lockup detectors) and so should be last resort. + */ +&watchdog { + timeout-sec = <32>; +};