From patchwork Fri May 9 13:00:08 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tushar Behera X-Patchwork-Id: 4143181 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B264F9F1E1 for ; Fri, 9 May 2014 13:02:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D9F04201C0 for ; Fri, 9 May 2014 13:02:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0131120142 for ; Fri, 9 May 2014 13:02:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756578AbaEINCG (ORCPT ); Fri, 9 May 2014 09:02:06 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:55396 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756220AbaEINCD (ORCPT ); Fri, 9 May 2014 09:02:03 -0400 Received: by mail-pa0-f49.google.com with SMTP id lj1so4347316pab.8 for ; Fri, 09 May 2014 06:02:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WCAePqJS2uwslKckclA05UfHO5YAaD7Qq2Mc89jLW6Q=; b=ayqvZSX7fqmVIIqGnaUaDrP2Caom3clCnHw+sJc2o3mpzA5whmMnItRk1VPeMysPkX l3nq485QzIl9E+BvU6XMl1A7jsKjNGnYFBDYtEH5HvP+lBmre5d8PVf4IUZmnop1nDCi UHpqwannULAUuqNX/nnDYz3Q0kurJDFGTQrx9mngDVC0/BjlmozBHapujIfp6q/CKRYf uaQMhNCscVxTR/cJzeLKbBH2qUo+reOoKsRbwdet8Cw/V2NzDkwMwz67DOC3mIRLeWlx dsiG6xoKvEI9Z8mQMmeV9qPDP/w0l9+JMyRWIOuUpDqbnpEagSAn3tqH8XwzfhLDxVCz LdfQ== X-Gm-Message-State: ALoCoQm+oUTcUS4vAVI+Nvz/5qV6p5imw+8xLlHlg33esqfamq2+4MQ6TVkv3UYVdKYVubpBhIH2 X-Received: by 10.66.227.104 with SMTP id rz8mr20381533pac.74.1399640523280; Fri, 09 May 2014 06:02:03 -0700 (PDT) Received: from linaro.sisodomain.com ([14.140.216.146]) by mx.google.com with ESMTPSA id qq5sm7556184pbb.24.2014.05.09.06.01.58 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 09 May 2014 06:02:02 -0700 (PDT) From: Tushar Behera To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, t.figa@samsung.com, kgene.kim@samsung.com, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: [PATCH 2/4] clk: samsung: exynos5420: Add xclkout debug clock Date: Fri, 9 May 2014 18:30:08 +0530 Message-Id: <1399640410-30957-3-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1399640410-30957-1-git-send-email-tushar.behera@linaro.org> References: <1399640410-30957-1-git-send-email-tushar.behera@linaro.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A new clock provider has been added to configure the XCLKOUT debug clock. Added a minimal implemetation for Exynos5420 clock driver. Right now, only one valid parent clock from XCLKOUT is defined in existing clock driver. The driver will be updated later for other for other parent clocks. Signed-off-by: Tushar Behera CC: Tomasz Figa --- drivers/clk/samsung/clk-exynos5420.c | 14 ++++++++++++++ include/dt-bindings/clock/exynos5420.h | 5 ++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 60b2681..a8f6527 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -296,6 +296,13 @@ PNAME(hdmi_p) = { "dout_hdmi_pixel", "sclk_hdmiphy" }; PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll", "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; +PNAME(xclkout_p) = { + "dummy", "dummy", "dummy", "dummy", + "dummy", "dummy", "dummy", "dummy", + "dummy", "dummy", "dummy", "dummy", + "dummy", "dummy", "dummy", "dummy", + "fin_pll", "dummy", "dummy" }; + /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), @@ -308,6 +315,7 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), + FRATE(0, "dummy", NULL, CLK_IS_ROOT, 0), }; static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { @@ -770,6 +778,10 @@ static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { KPLL_CON0, NULL), }; +static struct samsung_out_clock exynos5420_clkout[] __initdata = { + CLKOUT(CLK_XCLKOUT, "xclkout", xclkout_p), +}; + static struct of_device_id ext_clk_match[] __initdata = { { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, { }, @@ -802,6 +814,8 @@ static void __init exynos5420_clk_init(struct device_node *np) ARRAY_SIZE(exynos5420_div_clks)); samsung_clk_register_gate(exynos5420_gate_clks, ARRAY_SIZE(exynos5420_gate_clks)); + samsung_clk_register_clkout(np, + exynos5420_clkout, ARRAY_SIZE(exynos5420_clkout)); exynos5420_clk_sleep_init(); } diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 5eefd88..28eca32 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -182,7 +182,10 @@ /* divider clocks */ #define CLK_DOUT_PIXEL 768 +/* debug clocks */ +#define CLK_XCLKOUT 896 + /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 769 +#define CLK_NR_CLKS 897 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */