From patchwork Wed May 14 01:11:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Abraham X-Patchwork-Id: 4171661 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1AFB79F271 for ; Wed, 14 May 2014 01:12:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 18EAC20222 for ; Wed, 14 May 2014 01:12:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 034462034A for ; Wed, 14 May 2014 01:12:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752190AbaENBMl (ORCPT ); Tue, 13 May 2014 21:12:41 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:51652 "EHLO mail-pa0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752187AbaENBMk (ORCPT ); Tue, 13 May 2014 21:12:40 -0400 Received: by mail-pa0-f45.google.com with SMTP id ey11so954480pad.4 for ; Tue, 13 May 2014 18:12:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mRBChvMi0VJOfrF6ZSeu99W6qLLHH7Lu0mSPu5+5wSM=; b=M/NNcQZ7kgm3YaAr/EmY+0FqrZnt6jOzvL47a+jwSoSFASoeM+cQaNO5DLRxKtzAkS BjTuyHine1brinDvvz4iHeuFmxDlNheehLPjt3HD2Snu+TSrGexDDnGMuS3fhJrCwBgS zDxz6b/K72099iwbUwBX0iD+JkhY1anxIUWbE4hR1dLNRe8HEIhwgbqJa+8i7bx9TjMO T16sUfXpDJyhqhx3aIz1N31PP94UoSyhnyyJqvmkobhOWNIn7/9OcoIS3TB5IBZhS83q Cmf3DMyy7hoPu7dINuCAnbJpd3rlMvUsS8GLuEWqmMY5Q3tMBLr/bVxIQjTWAKY3IoAn smzw== X-Received: by 10.68.203.39 with SMTP id kn7mr377575pbc.141.1400029960043; Tue, 13 May 2014 18:12:40 -0700 (PDT) Received: from localhost.localdomain ([117.213.250.141]) by mx.google.com with ESMTPSA id tg9sm303528pbc.29.2014.05.13.18.12.27 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 13 May 2014 18:12:38 -0700 (PDT) X-Google-Original-From: Thomas Abraham From: Thomas Abraham To: cpufreq@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, shawn.guo@linaro.org, devicetree@vger.kernel.org, rjw@rjwysocki.net, linux-samsung-soc@vger.kernel.org, kgene.kim@samsung.com, t.figa@samsung.com, l.majewski@samsung.com, viresh.kumar@linaro.org, heiko@sntech.de, thomas.ab@samsung.com, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Subject: [PATCH v4 4/8] Documentation: devicetree: add cpu clock configuration data binding for Exynos4/5 Date: Wed, 14 May 2014 06:41:12 +0530 Message-Id: <1400029876-5830-5-git-send-email-thomas.ab@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1400029876-5830-1-git-send-email-thomas.ab@samsung.com> References: <1400029876-5830-1-git-send-email-thomas.ab@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From; Thomas Abraham The clock blocks within the CMU_CPU clock domain are put together into a new composite clock type called the cpu clock. This clock type requires configuration data that will be atomically programmed in the multiple clock blocks encapsulated within the cpu clock type when the parent clock frequency is changed. This configuration data is held in the clock controller node. Update clock binding documentation about this configuration data format for Samsung Exynos4 and Exynos5 platforms. Cc: Tomasz Figa Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Signed-off-by: Thomas Abraham --- .../devicetree/bindings/clock/exynos4-clock.txt | 37 ++++++++++++++++++++ .../devicetree/bindings/clock/exynos5250-clock.txt | 36 +++++++++++++++++++ 2 files changed, 73 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index f5a5b19..0934e02 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -15,6 +15,35 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + - for Exynos4210 and Exynos4212 based platforms: + cell #1: arm clock parent frequency + cell #2 ~ cell 9#: value of clock divider in the following order + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio. + + - for Exynos4412 based platforms: + cell #1: expected arm clock parent frequency + cell #2 ~ cell #10: value of clock divider in the following order + corem0_ratio, corem1_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio, cores_ratio + +- samsung,armclk-cells: defines the number of cells in + samsung,armclk-divider-table property. The value of this property depends on + the SoC type. + + - for Exynos4210 and Exynos4212: the value should be 9. + - for Exynos4412: the value should be 10. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -28,6 +57,14 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos4210-clock"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1200000 3 7 3 4 1 7 5 0>, + <1000000 3 7 3 4 1 7 4 0>, + < 800000 3 7 3 3 1 7 3 0>, + < 500000 3 7 3 3 1 7 3 0>, + < 400000 3 7 3 3 1 7 3 0>, + < 200000 1 3 1 1 1 0 3 0>; }; Example 2: UART controller node that consumes the clock generated by the clock diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 536eacd..3d63d09 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -13,6 +13,24 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + cell #1: expected arm clock parent frequency + cell #2 ~ cell #9: value of clock divider in the following order + cpud_ratio, acp_ratio, periph_ratio, atb_ratio, + pclk_dbg_ratio, apll_ratio, copy_ratio, hpm_ratio + +- samsung,armclk-cells: defines the number of cells in + samsung,armclk-divider-table property. The value of this property should be 9. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -26,6 +44,24 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1700000 3 7 7 7 3 5 0 2>, + <1600000 3 7 7 7 1 4 0 2>, + <1500000 2 7 7 7 1 4 0 2>, + <1400000 2 7 7 6 1 4 0 2>, + <1300000 2 7 7 6 1 3 0 2>, + <1200000 2 7 7 5 1 3 0 2>, + <1100000 3 7 7 5 1 3 0 2>, + <1000000 1 7 7 4 1 2 0 2>, + < 900000 1 7 7 4 1 2 0 2>, + < 800000 1 7 7 4 1 2 0 2>, + < 700000 1 7 7 3 1 1 0 2>, + < 600000 1 7 7 3 1 1 0 2>, + < 500000 1 7 7 2 1 1 0 2>, + < 400000 1 7 7 2 1 1 0 2>, + < 300000 1 7 7 1 1 1 0 2>, + < 200000 1 7 7 1 1 1 0 2>; }; Example 2: UART controller node that consumes the clock generated by the clock