From patchwork Fri May 16 12:23:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 4190831 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6E3F59F387 for ; Fri, 16 May 2014 12:25:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7E527202EC for ; Fri, 16 May 2014 12:25:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8967120272 for ; Fri, 16 May 2014 12:25:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754838AbaEPMZ3 (ORCPT ); Fri, 16 May 2014 08:25:29 -0400 Received: from mail-ee0-f45.google.com ([74.125.83.45]:53416 "EHLO mail-ee0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754537AbaEPMZ2 (ORCPT ); Fri, 16 May 2014 08:25:28 -0400 Received: by mail-ee0-f45.google.com with SMTP id d49so1501549eek.4 for ; Fri, 16 May 2014 05:25:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=z6YvaJkbjqpsV/NEDe6fleI6t4rg9U3mvFIdbCSfL/Q=; b=YnZcXHvInA1QPBmdBkhJHgTD7ld7Uh9f2tcYTf2NU3J6xbHqo1In9rAlPsNKxMwNBm Gs0IlETrRYoa69F9+vfgwS0RW6iu/nuYR+waUL1Tfa4aE5aN341ZPHB1GttCbSLPaBvx 722r9IfMkSkz+PcWvTsdj/SOFwILnECbfhdwylhXz4Z4QQK4QTyHGY1SP8FnKAERardB ZDzSTxo+RZjKd4fGUZTdhx9o1EALNjITAa3ggAsBLHm1ST+DtqdyVglizxCkPbvC6MqD R2aQ27eBlTARHUPK/yAFGYLGh4FD8IvhhHNeouJKSC8SvO7DseL6Sl0oMHzA5OZ3UY1m xI0Q== X-Received: by 10.15.67.142 with SMTP id u14mr22194567eex.19.1400243126011; Fri, 16 May 2014 05:25:26 -0700 (PDT) Received: from localhost (port-90043.pppoe.wtnet.de. [84.46.64.44]) by mx.google.com with ESMTPSA id x42sm19711448eel.41.2014.05.16.05.25.24 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 May 2014 05:25:25 -0700 (PDT) From: Thierry Reding To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Cc: Arnd Bergmann , Cho KyongHo , Grant Grundler , Dave Martin , Marc Zyngier , Will Deacon , Joerg Roedel , Stephen Warren , devicetree@vger.kernel.org, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] devicetree: Add generic IOMMU device tree bindings Date: Fri, 16 May 2014 14:23:18 +0200 Message-Id: <1400242998-437-1-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 1.9.2 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding This commit introduces a generic device tree binding for IOMMU devices. Only a very minimal subset is described here, but it is enough to cover the requirements of both the Exynos System MMU and Tegra SMMU as discussed here: https://lkml.org/lkml/2014/4/27/346 More advanced functionality such as the dma-ranges property can easily be added in a backwards-compatible way. In the absence of a dma-ranges property it should be safe to default to the whole address space. Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/iommu/iommu.txt | 109 ++++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/iommu.txt diff --git a/Documentation/devicetree/bindings/iommu/iommu.txt b/Documentation/devicetree/bindings/iommu/iommu.txt new file mode 100644 index 000000000000..2d67b52b656e --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/iommu.txt @@ -0,0 +1,109 @@ +This document describes the generic device tree binding for IOMMUs and their +master(s). + + +IOMMU device node: +================== + +An IOMMU can provide the following services: + +* Remap address space to allow devices to access physical memory ranges that + they otherwise wouldn't be capable of accessing. + + Example: 32-bit DMA to 64-bit physical addresses + +* Implement scatter-gather at page level granularity so that the device does + not have to. + +* Provide system protection against "rogue" DMA by forcing all accesses to go + through the IOMMU and faulting when encountering accesses to unmapped + address regions. + +* Provide address space isolation between multiple contexts. + + Example: Virtualization + +Device nodes compatible with this binding represent hardware with some of the +above capabilities. + +IOMMUs can be single-master or multiple-master. Single-master IOMMU devices +typically have a fixed association to the master device, whereas multiple- +master IOMMU devices can translate accesses from more than one master. + +Required properties: +-------------------- +- #iommu-cells: The number of cells in an IOMMU specifier. The meaning of the + cells is defined by the binding for the IOMMU device. + + Typical values include: + * 0: Single-master IOMMU devices are often not configurable, therefore the + specifying doesn't need to encode any information and can be empty. + + * 1: Multiple-master IOMMU devices need to know for which master they should + enable translation. Typically the single cell in the specifier corresponds + to the master device's ID. + + +IOMMU master node: +================== + +Devices that access memory through an IOMMU are called masters. A device can +have multiple master interfaces (to one or more IOMMU devices). + +Required properties: +-------------------- +- iommus: A list of phandle and IOMMU specifier pairs that describe the IOMMU + master interfaces of the device. One entry in the list describes one master + interface of the device. + +Optional properties: +-------------------- +- iommu-names: A list of names identifying each entry in the iommus property. + + +Examples: +========= + +Single-master IOMMU: +-------------------- + + iommu { + #iommu-cells = <0>; + }; + + master { + iommu = <&/iommu>; + }; + +Multi-master IOMMU: +------------------- + + iommu { + /* the specifier represents the ID of the master */ + #iommu-cells = <1>; + }; + + master { + /* device has master ID 42 in the IOMMU */ + iommu = <&/iommu 42>; + }; + +Multi-master device: +-------------------- + + /* single-master IOMMU */ + iommu@1 { + #iommu-cells = <0>; + }; + + /* multi-master IOMMU */ + iommu@2 { + /* the specifier represents the ID of the master */ + #iommu-cells = <1>; + }; + + /* device with two master interfaces */ + master { + iommus = <&/iommu@1>, /* master of the single-master IOMMU */ + <&/iommu@2 42>; /* ID 42 in multi-master IOMMU */ + };