@@ -32,10 +32,51 @@ static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)
xhci->quirks |= XHCI_PLAT;
}
+static int xhci_plat_calibrate_phy(struct xhci_hcd *xhci)
+{
+ int ret = 0;
+ struct usb_hcd *hcd = xhci_to_hcd(xhci);
+
+ /* calibrate phy if available */
+ if (!IS_ERR(xhci->phy2_gen)) {
+ ret = phy_calibrate(xhci->phy2_gen);
+ if (ret < 0 && ret != -ENOTSUPP) {
+ dev_err(hcd->self.controller,
+ "failed to calibrate USB 2.0 type PHY\n");
+ return ret;
+ }
+ }
+
+ if (!IS_ERR(xhci->phy3_gen)) {
+ ret = phy_calibrate(xhci->phy3_gen);
+ if (ret < 0 && ret != -ENOTSUPP)
+ dev_err(hcd->self.controller,
+ "failed to calibrate USB 3.0 type PHY\n");
+ }
+
+ return ret;
+}
+
/* called during probe() after chip reset completes */
static int xhci_plat_setup(struct usb_hcd *hcd)
{
- return xhci_gen_setup(hcd, xhci_plat_quirks);
+ struct xhci_hcd *xhci;
+ int ret;
+
+ ret = xhci_gen_setup(hcd, xhci_plat_quirks);
+ if (ret) {
+ dev_err(hcd->self.controller, "xhci setup failed\n");
+ return ret;
+ }
+
+ if (!usb_hcd_is_primary_hcd(hcd)) {
+ xhci = hcd_to_xhci(hcd);
+ ret = xhci_plat_calibrate_phy(xhci);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
static int xhci_plat_start(struct usb_hcd *hcd)
@@ -276,8 +317,13 @@ static int xhci_plat_resume(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+ int ret;
+
+ ret = xhci_resume(xhci, 0);
+ if (ret)
+ return ret;
- return xhci_resume(xhci, 0);
+ return xhci_plat_calibrate_phy(xhci);
}
static const struct dev_pm_ops xhci_plat_pm_ops = {
Some quirky PHYs may require to be calibrated post the host controller initialization. The USB 3.0 DRD PHY on Exynos5420/5800 systems is one such PHY which needs to calibrated post xhci's reset at initialization time and at resume time, to get the controller work at SuperSpeed. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> --- drivers/usb/host/xhci-plat.c | 50 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-)