From patchwork Wed Jun 25 13:37:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 4420821 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A139D9F390 for ; Wed, 25 Jun 2014 13:39:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C7E9520158 for ; Wed, 25 Jun 2014 13:39:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B44982038F for ; Wed, 25 Jun 2014 13:39:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754073AbaFYNjg (ORCPT ); Wed, 25 Jun 2014 09:39:36 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:30113 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756736AbaFYNiU (ORCPT ); Wed, 25 Jun 2014 09:38:20 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N7Q00NR88JR3Z10@mailout1.w1.samsung.com>; Wed, 25 Jun 2014 14:38:15 +0100 (BST) X-AuditID: cbfec7f4-b7fac6d000006cfe-5f-53aad0cbb721 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 83.9B.27902.BC0DAA35; Wed, 25 Jun 2014 14:38:19 +0100 (BST) Received: from AMDC1227.digital.local ([106.116.147.199]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0N7Q00AH88JOVV90@eusync2.samsung.com>; Wed, 25 Jun 2014 14:38:19 +0100 (BST) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Kukjin Kim , Laura Abbott , Linus Walleij , Russell King - ARM Linux , Santosh Shilimkar , Tony Lindgren , Tomasz Figa , Daniel Drake , Marek Szyprowski , Tomasz Figa Subject: [PATCH v2 6/6] ARM: dts: exynos4: Add nodes for L2 cache controller Date: Wed, 25 Jun 2014 15:37:31 +0200 Message-id: <1403703451-12233-7-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.9.3 In-reply-to: <1403703451-12233-1-git-send-email-t.figa@samsung.com> References: <1403703451-12233-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHLMWRmVeSWpSXmKPExsVy+t/xK7qnL6wKNjh8ndXi0fzHzBa9C66y WWzvnMFuMeXPciaLTY+vsVpc3jWHzWL2kn4Wixnn9zFZ3L7Ma7H2yF12i9d9a5gt1s94zWKx atcfRov9V7wc+DxamnvYPL59ncTicbmvl8lj0fcsj52z7rJ73Lm2h81j85J6j74tqxg9jt/Y zuTxeZNcAFcUl01Kak5mWWqRvl0CV8bFnk7WgoM8FdOuvGNsYJzP1cXIySEhYCJxrLmdGcIW k7hwbz1bFyMXh5DAUkaJSefusUA4fUwSa6/cYAOpYhNQk/jc8AjMFhFQlfjctoAdpIhZoIFF 4krrdbCEsICPxNRdK8HGsgAVrZ09j7WLkYODV8BJouWbMMQ2OYnebW/ASjgFnCUuzPvDCmIL AZXMe3KEcQIj7wJGhlWMoqmlyQXFSem5hnrFibnFpXnpesn5uZsYIWH8ZQfj4mNWhxgFOBiV eHgDeFYFC7EmlhVX5h5ilOBgVhLhdd8PFOJNSaysSi3Kjy8qzUktPsTIxMEp1cDoZ/7I/MaG zRIed39NV9zkd1yxbHZmh6pLzYcXcW2/l0316k0MvSa74senTa0yIWrXWLOWzjNlO+PyxbLd XCGu/6pG7oJl3Wa82z+rnVz2d61BtfzraFlBuwK9az+0j9uJ3EudXPBCcemKK/Lup4wePaoW 0J7bdyfC+tqPycyTd7AcK20zOy6jxFKckWioxVxUnAgAJlbnh0ECAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa --- arch/arm/boot/dts/exynos4210.dtsi | 9 +++++++++ arch/arm/boot/dts/exynos4x12.dtsi | 14 ++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index ee3001f..99970ab 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -54,6 +54,15 @@ reg = <0x10023CA0 0x20>; }; + l2c: l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <2 2 1>; + }; + gic: interrupt-controller@10490000 { cpu-offset = <0x8000>; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index c5a943d..ddffefe 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -60,6 +60,20 @@ reg = <0x10023CA0 0x20>; }; + l2c: l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <3 2 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <1>; + arm,prefetch-offset = <7>; + }; + clock: clock-controller@10030000 { compatible = "samsung,exynos4412-clock"; reg = <0x10030000 0x20000>;