From patchwork Wed Jul 30 14:36:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Humberto Naves X-Patchwork-Id: 4649831 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1C919C0338 for ; Wed, 30 Jul 2014 14:36:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2BE8520149 for ; Wed, 30 Jul 2014 14:36:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 231FF20122 for ; Wed, 30 Jul 2014 14:36:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753511AbaG3OgT (ORCPT ); Wed, 30 Jul 2014 10:36:19 -0400 Received: from mail-wi0-f174.google.com ([209.85.212.174]:62596 "EHLO mail-wi0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752834AbaG3OgT (ORCPT ); Wed, 30 Jul 2014 10:36:19 -0400 Received: by mail-wi0-f174.google.com with SMTP id d1so7698055wiv.1 for ; Wed, 30 Jul 2014 07:36:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HDNz22lBKuqC6LjpJuhA54huDeJBMSE179ns1JSF5uw=; b=UYcs2GmK7ZpyVl7qugEc/fQ7SqCCWHjbCQDL4+jaVx3NUr2LQYY7zdwF8epjx9S4El 92QW7727j/veZVQHwTWGaEsdhW9VBomu/RzNQuNdLDeeWFoo0RlqjTEeRVtpFX0P240D rGuVSPpR7IhXV66bX4FQMGU1Q5bggEE2jOYeuO4j+zZxuHxGYtwLDsQezH0P2IiEy0t8 +iulyEcnPiG0h05x2pA9JiGaY7U3W18EeZVacqBrIT8l8jsX90/OZ+KhuRbAA++OEnUL 0Kv7OBMwAP1OEJdzNqjCqIPj9MwQaZHtSPKlmFkCW++6PoivUMKDEsvVrufv5KC6ry45 Z25A== X-Received: by 10.180.208.81 with SMTP id mc17mr7649892wic.7.1406730976241; Wed, 30 Jul 2014 07:36:16 -0700 (PDT) Received: from localhost.localdomain (84-73-200-99.dclient.hispeed.ch. [84.73.200.99]) by mx.google.com with ESMTPSA id ek3sm5978732wjd.17.2014.07.30.07.36.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Jul 2014 07:36:15 -0700 (PDT) From: Humberto Silva Naves To: linux-samsung-soc@vger.kernel.org Cc: Tomasz Figa , Humberto Silva Naves Subject: [PATCH 2/3] clk: exynos5410: Add suspend/resume handling Date: Wed, 30 Jul 2014 16:36:02 +0200 Message-Id: <1406730963-30658-2-git-send-email-hsnaves@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1406730963-30658-1-git-send-email-hsnaves@gmail.com> References: <1406730963-30658-1-git-send-email-hsnaves@gmail.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch implements all the necessary code that handles register saving and restoring during a suspend/resume cycle. To make this possible, the local variable reg_base from the function exynos5410_clk_init was changed to global. Signed-off-by: Humberto Silva Naves Reviewed-by: Thomas Abraham --- drivers/clk/samsung/clk-exynos5410.c | 132 +++++++++++++++++++++++++++++++++- 1 file changed, 131 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 72a533e..aaca65d 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "clk.h" @@ -160,6 +161,134 @@ enum exynos5410_plls { nr_plls /* number of PLLs */ }; +static void __iomem *reg_base; + +#ifdef CONFIG_PM_SLEEP +static struct samsung_clk_reg_dump *exynos5410_save; + +/* + * list of controller registers to be saved and restored during a + * suspend/resume cycle. + */ +static unsigned long exynos5410_clk_regs[] __initdata = { + SRC_CDREX, + SRC_CPERI0, + SRC_CPERI1, + SRC_CPU, + SRC_DISP0_0, + SRC_DISP0_1, + SRC_DISP1_0, + SRC_DISP1_1, + SRC_FSYS, + SRC_GSCL, + SRC_KFC, + SRC_MAU, + SRC_PERIC0, + SRC_PERIC1, + SRC_TOP0, + SRC_TOP1, + SRC_TOP2, + SRC_TOP3, + + DIV_CDREX, + DIV_CDREX2, + DIV_CPU0, + DIV_CPERI1, + DIV_DISP0_0, + DIV_DISP0_1, + DIV_DISP1_0, + DIV_DISP1_1, + DIV_FSYS0, + DIV_FSYS1, + DIV_FSYS2, + DIV_GEN, + DIV_GSCL, + DIV_G2D, + DIV_KFC0, + DIV_MAU, + DIV_PERIC0, + DIV_PERIC1, + DIV_PERIC2, + DIV_PERIC3, + DIV_PERIC4, + DIV_PERIC5, + DIV_TOP0, + DIV_TOP1, + DIV_TOP2, + DIV_TOP3, + + GATE_BUS_DISP1, + GATE_BUS_FSYS0, + + GATE_IP_CDREX, + GATE_IP_CORE, + GATE_IP_DISP0, + GATE_IP_DISP1, + GATE_IP_FSYS, + GATE_IP_GEN, + GATE_IP_GSCL0, + GATE_IP_GSCL1, + GATE_IP_G2D, + GATE_IP_G3D, + GATE_IP_MFC, + GATE_IP_PERIC, + GATE_IP_PERIS, + + GATE_TOP_SCLK_DISP1, + GATE_TOP_SCLK_FSYS, + GATE_TOP_SCLK_GSCL, + GATE_TOP_SCLK_MAU, + GATE_TOP_SCLK_PERIC, + + GATE_BUS_DISP1, + GATE_BUS_FSYS0, + + GATE_SCLK_CPU, + + SRC_MASK_DISP0_0, + SRC_MASK_DISP1_0, + SRC_MASK_FSYS, + SRC_MASK_MAU, + SRC_MASK_PERIC0, + SRC_MASK_PERIC1, +}; + +static int exynos5410_clk_suspend(void) +{ + samsung_clk_save(reg_base, exynos5410_save, + ARRAY_SIZE(exynos5410_clk_regs)); + + return 0; +} + +static void exynos5410_clk_resume(void) +{ + samsung_clk_restore(reg_base, exynos5410_save, + ARRAY_SIZE(exynos5410_clk_regs)); +} + +static struct syscore_ops exynos5410_clk_syscore_ops = { + .suspend = exynos5410_clk_suspend, + .resume = exynos5410_clk_resume, +}; + +static void exynos5410_clk_sleep_init(void) +{ + exynos5410_save = samsung_clk_alloc_reg_dump(exynos5410_clk_regs, + ARRAY_SIZE(exynos5410_clk_regs)); + if (!exynos5410_save) { + pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", + __func__); + return; + } + + register_syscore_ops(&exynos5410_clk_syscore_ops); +} +#else +static void exynos5410_clk_sleep_init(void) {} +#endif + + /* list of all parent clocks */ PNAME(apll_p) = { "fin_pll", "fout_apll", }; PNAME(bpll_p) = { "fin_pll", "fout_bpll", }; @@ -286,7 +415,6 @@ static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = { static void __init exynos5410_clk_init(struct device_node *np) { struct samsung_clk_provider *ctx; - void __iomem *reg_base; reg_base = of_iomap(np, 0); if (!reg_base) @@ -304,6 +432,8 @@ static void __init exynos5410_clk_init(struct device_node *np) samsung_clk_register_gate(ctx, exynos5410_gate_clks, ARRAY_SIZE(exynos5410_gate_clks)); + exynos5410_clk_sleep_init(); + samsung_clk_of_add_provider(np, ctx); pr_debug("Exynos5410: clock setup completed.\n");