diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
new file mode 100644
index 0000000..c361525
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -0,0 +1,209 @@
+* Samsung Exynos7 Clock Controller
+
+Exynos7 clock controller has 25 blocks which are instantiated
+independently from the device-tree. These clock controllers
+generate and supply clocks to various hardware blocks within
+the SoC.
+
+Each clock is assigned an identifier and client nodes can use
+this identifier to specify the clock which they consume. All
+available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos7-clk.h header and can be used in
+device tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It
+is expected that they are defined using standard clock bindings
+with following clock-output-names:
+
+ - "fin_pll" - PLL input clock from XXTI
+
+Phy clocks:
+
+There are several clocks which are generated by specific PHYs.
+These clocks are fed into the clock controller and then routed to
+the hardware blocks. These clocks are defined as fixed clocks in the
+driver with following names:
+
+Required Properties for Clock Controller:
+
+ - compatible: should be one of the following.
+	1) "samsung,exynos7-clock-topc"
+	2) "samsung,exynos7-clock-top0"
+	3) "samsung,exynos7-clock-top1"
+	4) "samsung,exynos7-clock-atlas"
+	5) "samsung,exynos7-clock-ccore"
+	6) "samsung,exynos7-clock-imem"
+	7) "samsung,exynos7-clock-g3d"
+	8) "samsung,exynos7-clock-mif0"
+	9) "samsung,exynos7-clock-mif1"
+	10) "samsung,exynos7-clock-mif2"
+	11) "samsung,exynos7-clock-mif3"
+	12) "samsung,exynos7-clock-peric0"
+	13) "samsung,exynos7-clock-peric1"
+	14) "samsung,exynos7-clock-peris"
+	15) "samsung,exynos7-clock-bus0"
+	16) "samsung,exynos7-clock-bus1"
+	17) "samsung,exynos7-clock-fsys0"
+	18) "samsung,exynos7-clock-fsys1"
+	19) "samsung,exynos7-clock-disp"
+	20) "samsung,exynos7-clock-aud"
+	21) "samsung,exynos7-clock-mscl"
+	22) "samsung,exynos7-clock-mfc"
+
+ - reg: physical base address of the controller and the length of
+	memory mapped region.
+
+ - #clock-cells: should be 1.
+
+ - clocks: list of clock identifiers which are fed as the input to
+	the given clock controller. Please refer the next section to find
+	the input clocks for a given controller.
+
+ - clock-names: list of names of clocks which are fed as the input
+	to the given clock controller.
+
+Input clocks for topc clock controller:
+	- fin_pll
+	- fout_aud_pll
+	- fout_bus0_pl
+	- fout_bus1_pl
+	- fout_cc_pll
+	- fout_mfc_pll
+	- dout_sclk_cmu_apbif
+
+Input clocks for top0 clock controller:
+	- fin_pll
+	- fout_mif01_pll
+	- sclk_bus0_pll_mif
+	- sclk_bus0_pll_a
+	- sclk_bus1_pll_a
+	- sclk_cc_pll_a
+	- sclk_mfc_pll_a
+	- sclk_aud_pll
+	- sclk_cmu_apbif
+	- ioclk_audiocdclk0
+	- ioclk_audiocdclk1
+	- ioclk_spdif_extclk
+
+Input clocks for top1 clock controller:
+	- fin_pll
+	- fout_mif23_pll
+	- sclk_bus0_pll_mif
+	- sclk_bus0_pll_b
+	- sclk_bus1_pll_b
+	- sclk_cc_pll_b
+	- sclk_mfc_pll_b
+	- sclk_cmu_apbif
+
+Input clocks for ccore clock controller:
+	- fin_pll
+	- aclk_ccore_532
+	- aclk_ccore_133
+
+Input clocks for peric0 clock controller:
+	- fin_pll
+	- aclk_peric0_66
+	- sclk_uart0
+
+Input clocks for peric1 clock controller:
+	- fin_pll
+	- aclk_peric01_66
+	- sclk_uart1
+	- sclk_uart2
+	- sclk_uart3
+	- sclk_spi0
+	- sclk_spi1
+	- sclk_spi2
+	- sclk_spi3
+	- sclk_spi4
+	- sclk_i2s1
+	- sclk_pcm1
+	- sclk_spdif
+	- ioclk_i2s1_bclk
+	- ioclk_spi0_clk
+	- ioclk_spi1_clk
+	- ioclk_spi2_clk
+	- ioclk_spi3_clk
+	- ioclk_spi4_clk
+
+Input clocks for peris clock controller:
+	- fin_pll
+	- aclk_peris_66
+	- rtclk (blk_rtc)
+
+Input clocks for bus0 clock controller:
+	- fin_pll
+	- aclk_bus0_532
+
+Input clocks for bus1 clock controller:
+	- fin_pll
+	- aclk_bus1_200
+	- aclk_bus1_532
+
+Input clocks for fsys0 clock controller:
+	- fin_pll
+	- fout_hsic_pll
+	- aclk_fsys0_200
+	- sclk_phy_fsys0_26m
+	- aclk_usbdrd200
+	- sclk_mmc2
+	- sclk_ufsunipro11
+	- sclk_phy_fsys0
+	- phyclk_usbdrd300_udrd30_phyclock
+	- phyclk_usbdrd300_udrd30_pipe_pclk
+	- phyclk_usbhost20_phy_freeclk_hsic1
+	- phyclk_usbhost20_phy_phyclk_hsic1
+	- phyclk_ufs_tx0_symbol
+	- phyclk_ufs_rx0_symbol
+	- phyclk_lli_tx0_symbol
+	- phyclk_lli_rx0_symbol
+	- phyclk_pcie_tx0
+	- phyclk_pcie_rx0
+
+Input clocks for fsys1 clock controller:
+	- fin_pll
+	- aclk_fsys1_200
+	- sclk_phy_fsys1_26m
+	- sclk_mmc0
+	- sclk_mmc1
+	- sclk_ufsunipro20
+	- sclk_phy_fsys1
+	- sclk_txl400_wifi1
+	- phyclk_ufs20_tx0_symbol
+	- phyclk_ufs20_rx0_symbol
+	- phyclk_ufs20_rx1_symbol
+	- phyclk_pcie_wifi1_tx0
+	- phyclk_pcie_wifi1_rx0
+
+Input clocks for disp clock controller:
+	- fin_pll
+	- fout_disp_pll
+	- fout_dphy_pll
+	- aclk_disp_400
+	- sclk_dsd
+	- sclk_hdmi_spdif
+	- sclk_decon_int_eclk
+	- sclk_decon_ext_eclk
+	- sclk_decon_vclk
+	- phyclk_mipidphy0_rxclkesc0
+	- phyclk_mipidphy0_bitclkdiv8
+	- phyclk_mipidphy1_rxclkesc0
+	- phyclk_mipidphy1_bitclkdiv8
+	- sclk_rgb_vclk_dsim0
+	- sclk_rgb_vclk_dsim1
+	- sclk_decon_ext_vclk
+	- phyclk_dpphy_ch3_txd_clk
+	- phyclk_dpphy_ch2_txd_clk
+	- phyclk_dpphy_ch1_txd_clk
+	- phyclk_dpphy_ch0_txd_clk
+	- phyclk_hdmi_phy_tmds_clko
+	- phyclk_hdmi_phy_pixel_clko
+
+Input clocks for audio clock controller:
+	- fin_pll
+	- fout_aud_pll
+	- ioclk_audiocdclk0
+	- ioclk_slimbus_clk
+	- ioclk_i2s_bclk
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc6..5da0ba9 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
 obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
 obj-$(CONFIG_ARCH_S3C64XX)	+= clk-s3c64xx.o
 obj-$(CONFIG_ARCH_S5PV210)	+= clk-s5pv210.o clk-s5pv210-audss.o
+obj-$(CONFIG_ARCH_EXYNOS7)	+= clk-exynos7.o
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
new file mode 100644
index 0000000..b62251f
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -0,0 +1,1929 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for TOP0, TOP1 and TOPC,
+ * CCORE, PERIC0, PERIC1 and PERIS, BUS0, BUS1, FSYS0, FSYS1,
+ * Multi media subsystems such as G3D, AUD, DISP, MSCL and
+ * MFC blocks of the Exynos7 clock controller.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+
+#include "clk.h"
+#include <dt-bindings/clock/exynos7-clk.h>
+
+/* PMS values for PLL 1451x */
+static const struct samsung_pll_rate_table pll1451x_24mhz_tbl[] = {
+	/* rate, m, p, s */
+	PLL_35XX_RATE(660000000, 165, 3, 1),
+	PLL_35XX_RATE(1800000000, 150, 2, 0),
+	PLL_35XX_RATE(1700000000, 425, 6, 0),
+	PLL_35XX_RATE(1600000000, 200, 3, 0),
+	PLL_35XX_RATE(1500000000, 125, 2, 0),
+	PLL_35XX_RATE(1400000000, 175, 3, 0),
+	PLL_35XX_RATE(1380000000, 115, 2, 0),
+	PLL_35XX_RATE(1300000000, 325, 6, 0),
+	PLL_35XX_RATE(1200000000, 100, 2, 0),
+	PLL_35XX_RATE(1180000000, 295, 6, 0),
+	PLL_35XX_RATE(1104000000, 276, 6, 0),
+	PLL_35XX_RATE(1100000000, 275, 6, 0),
+	PLL_35XX_RATE(1064000000, 133, 3, 0),
+	PLL_35XX_RATE(1000000000, 125, 3, 0),
+	PLL_35XX_RATE(932000000, 233, 6, 0),
+	PLL_35XX_RATE(900000000, 150, 2, 1),
+	PLL_35XX_RATE(825000000, 275, 4, 1),
+	PLL_35XX_RATE(800000000, 200, 3, 1),
+	PLL_35XX_RATE(750000000, 125, 2, 1),
+	PLL_35XX_RATE(700000000, 175, 3, 1),
+	PLL_35XX_RATE(690000000, 115, 2, 1),
+	PLL_35XX_RATE(668000000, 167, 3, 1),
+	PLL_35XX_RATE(600000000, 100, 2, 1),
+	PLL_35XX_RATE(590000000, 295, 6, 1),
+	PLL_35XX_RATE(552000000, 92,  2, 1),
+	PLL_35XX_RATE(532000000, 133, 3, 1),
+	PLL_35XX_RATE(500000000, 125, 3, 1),
+	PLL_35XX_RATE(492000000, 82,  2, 1),
+	PLL_35XX_RATE(468000000, 78,  2, 1),
+	PLL_35XX_RATE(450000000, 150, 2, 2),
+	PLL_35XX_RATE(432000000, 144, 2, 2),
+	PLL_35XX_RATE(420000000, 140, 2, 2),
+	PLL_35XX_RATE(400000000, 200, 3, 2),
+	PLL_35XX_RATE(368000000, 184, 3, 2),
+	PLL_35XX_RATE(350000000, 175, 3, 2),
+	PLL_35XX_RATE(334000000, 167, 3, 2),
+	PLL_35XX_RATE(300000000, 100, 2, 2),
+	PLL_35XX_RATE(276000000, 92,  2, 2),
+	PLL_35XX_RATE(266000000, 133, 3, 2),
+	PLL_35XX_RATE(233000000, 233, 6, 2),
+	PLL_35XX_RATE(200000000, 200, 3, 3),
+	PLL_35XX_RATE(177000000, 118, 2, 3),
+	PLL_35XX_RATE(167000000, 167, 3, 3),
+	PLL_35XX_RATE(150000000, 100, 2, 3),
+	PLL_35XX_RATE(133000000, 133, 3, 3),
+	PLL_35XX_RATE(100000000, 200, 3, 4),
+	PLL_35XX_RATE(84000000, 112, 2, 4),
+	PLL_35XX_RATE(75000000, 100, 2, 4),
+	PLL_35XX_RATE(66000000, 88, 2, 4),
+};
+
+/* PMS values for PLL 1452x */
+static const struct samsung_pll_rate_table pll1452x_24mhz_tbl[] = {
+	/* rate, m, p, s */
+	PLL_35XX_RATE(260000000, 130, 6, 1),
+	PLL_35XX_RATE(480000000, 240, 6, 1),
+	PLL_35XX_RATE(652000000, 163, 6, 0),
+	PLL_35XX_RATE(1000000000, 250, 6, 0),
+	PLL_35XX_RATE(932000000, 233, 6, 0),
+	PLL_35XX_RATE(900000000, 225, 6, 0),
+	PLL_35XX_RATE(800000000, 200, 6, 0),
+	PLL_35XX_RATE(752000000, 188, 6, 0),
+	PLL_35XX_RATE(700000000, 175, 6, 0),
+	PLL_35XX_RATE(692000000, 173, 6, 0),
+	PLL_35XX_RATE(668000000, 167, 6, 0),
+	PLL_35XX_RATE(600000000, 150, 6, 0),
+	PLL_35XX_RATE(592000000, 148, 6, 0),
+	PLL_35XX_RATE(552000000, 138, 6, 0),
+	PLL_35XX_RATE(532000000, 133, 6, 0),
+	PLL_35XX_RATE(500000000, 250, 6, 1),
+	PLL_35XX_RATE(492000000, 246, 6, 1),
+	PLL_35XX_RATE(468000000, 234, 6, 1),
+	PLL_35XX_RATE(450000000, 225, 6, 1),
+	PLL_35XX_RATE(432000000, 216, 6, 1),
+	PLL_35XX_RATE(420000000, 210, 6, 1),
+	PLL_35XX_RATE(400000000, 200, 6, 1),
+	PLL_35XX_RATE(368000000, 184, 6, 1),
+	PLL_35XX_RATE(350000000, 175, 6, 1),
+	PLL_35XX_RATE(334000000, 167, 6, 1),
+	PLL_35XX_RATE(300000000, 150, 6, 1),
+	PLL_35XX_RATE(276000000, 138, 6, 1),
+	PLL_35XX_RATE(266000000, 133, 6, 1),
+	PLL_35XX_RATE(233000000, 233, 6, 2),
+	PLL_35XX_RATE(200000000, 200, 6, 2),
+	PLL_35XX_RATE(177000000, 177, 6, 2),
+	PLL_35XX_RATE(167000000, 167, 6, 2),
+	PLL_35XX_RATE(150000000, 150, 6, 2),
+	PLL_35XX_RATE(133000000, 133, 6, 2),
+	PLL_35XX_RATE(100000000, 200, 6, 3),
+	PLL_35XX_RATE(84000000, 168, 6, 3),
+	PLL_35XX_RATE(75000000, 150, 6, 3),
+	PLL_35XX_RATE(66000000, 132, 6, 3),
+};
+
+/* PMS values for PLL 1460x */
+static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] = {
+	/* rate, m, p, s, k */
+	PLL_36XX_RATE(96000000, 32, 1, 3, 0),
+	PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
+	PLL_36XX_RATE(396000000, 33, 1, 1, 0),
+	PLL_36XX_RATE(393216000, 33, 1, 1, -15204),
+	PLL_36XX_RATE(384000000, 32, 1, 1, 0),
+	PLL_36XX_RATE(368640000, 31, 1, 1, -18350),
+	PLL_36XX_RATE(361507000, 30, 1, 1, 8231),
+	PLL_36XX_RATE(338668000, 28, 1, 1, 14571),
+	PLL_36XX_RATE(294912000, 25, 1, 1, -27787),
+	PLL_36XX_RATE(288000000, 24, 1, 1, 0),
+	PLL_36XX_RATE(252000000, 21, 1, 1, 0),
+	PLL_36XX_RATE(800000000, 33, 1, 0, 21845),
+	PLL_36XX_RATE(750000000, 31, 1, 0, 16384),
+	PLL_36XX_RATE(700000000, 29, 1, 0, 10923),
+	PLL_36XX_RATE(690000000, 29, 1, 0, -16384),
+	PLL_36XX_RATE(668000000, 28, 1, 0, -10923),
+	PLL_36XX_RATE(600000000, 25, 1, 0, 0),
+	PLL_36XX_RATE(590000000, 25, 1, 0, -27307),
+	PLL_36XX_RATE(552000000, 23, 1, 0, 0),
+	PLL_36XX_RATE(532000000, 22, 1, 0, 10923),
+	PLL_36XX_RATE(500000000, 21, 1, 0, -10923),
+	PLL_36XX_RATE(492000000, 21, 1, 0, -32768),
+	PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
+	PLL_36XX_RATE(468000000, 20, 1, 0, -32768),
+	PLL_36XX_RATE(450000000, 19, 1, 0, -16384),
+	PLL_36XX_RATE(432000000, 18, 1, 0, 0),
+	PLL_36XX_RATE(420000000, 18, 1, 0, -32768),
+	PLL_36XX_RATE(400000000, 33, 1, 1, 21845),
+	PLL_36XX_RATE(396000000, 33, 1, 1, 0),
+	PLL_36XX_RATE(393216000, 33, 1, 1, -15204),
+	PLL_36XX_RATE(384000000, 32, 1, 1, 0),
+	PLL_36XX_RATE(368640000, 31, 1, 1, -18350),
+	PLL_36XX_RATE(368000000, 31, 1, 1, -21845),
+	PLL_36XX_RATE(361507000, 30, 1, 1, 8231),
+	PLL_36XX_RATE(350000000, 29, 1, 1, 10923),
+	PLL_36XX_RATE(338638000, 28, 1, 1, 14571),
+	PLL_36XX_RATE(334000000, 28, 1, 1, -10923),
+	PLL_36XX_RATE(300000000, 25, 1, 1, 0),
+	PLL_36XX_RATE(294912000, 25, 1, 1, -27787),
+	PLL_36XX_RATE(288000000, 24, 1, 1, 0),
+	PLL_36XX_RATE(276000000, 23, 1, 1, 0),
+	PLL_36XX_RATE(266000000, 22, 1, 1, 10923),
+	PLL_36XX_RATE(252000000, 21, 1, 1, 0),
+	PLL_36XX_RATE(233000000, 19, 1, 1, 27307),
+	PLL_36XX_RATE(200000000, 33, 1, 2, 21845),
+	PLL_36XX_RATE(177000000, 30, 1, 2, -32768),
+	PLL_36XX_RATE(167000000, 28, 1, 2, -10923),
+	PLL_36XX_RATE(150000000, 25, 1, 2, 0),
+	PLL_36XX_RATE(133000000, 22, 1, 2, 10923),
+	PLL_36XX_RATE(100000000, 33, 1,  3, 21845),
+	PLL_36XX_RATE(84000000, 28, 1, 3, 0),
+	PLL_36XX_RATE(75000000, 25, 1, 3, 0),
+	PLL_36XX_RATE(66000000, 22, 1, 3, 0),
+};
+
+/* Register Offset definitions for CMU_TOPC (0x10570000) */
+#define	CC_PLL_LOCK			0x0000
+#define	BUS0_PLL_LOCK			0x0004
+#define	BUS1_DPLL_LOCK			0x0008
+#define	MFC_PLL_LOCK			0x000C
+#define	AUD_PLL_LOCK			0x0010
+#define	MIF_PLL_LOCK			0x0014
+#define	CC_PLL_CON0			0x0100
+#define	CC_PLL_CON1			0x0104
+#define	BUS0_PLL_CON0			0x0110
+#define	BUS0_PLL_CON1			0x0114
+#define	BUS1_DPLL_CON0			0x0120
+#define	BUS1_DPLL_CON1			0x0124
+#define	MFC_PLL_CON0			0x0130
+#define	MFC_PPL_CON1			0x0134
+#define	AUD_PLL_CON0			0x0140
+#define	AUD_PLL_CON1			0x0144
+#define	AUD_PLL_CON2			0x0148
+#define	MIF_PLL_CON0			0x0150
+#define	MIF_PLL_CON1			0x0154
+#define	MIF_PLL_CON2			0x0158
+#define	MUX_SEL_TOPC0			0x0200
+#define	MUX_SEL_TOPC1			0x0204
+#define	MUX_SEL_TOPC2			0x0208
+#define	MUX_SEL_TOPC3			0x020C
+#define	MUX_SEL_TOPC4			0x0210
+#define	MUX_SEL_TOPC5			0x0214
+#define	DIV_TOPC0			0x0600
+#define	DIV_TOPC1			0x0604
+#define	DIV_TOPC2			0x0608
+#define	DIV_TOPC3			0x060C
+#define	ENABLE_ACLK_TOPC0		0x0800
+#define	ENABLE_ACLK_TOPC1		0x0804
+#define	ENABLE_ACLK_TOPC2		0x0808
+#define	ENABLE_SCLK_TOPC0		0x0A00
+#define	ENABLE_SCLK_TOPC1		0x0A04
+
+static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
+	FFACTOR(0, "ffac_topc_bus0_pll_div2",
+			"mout_bus0_pll_ctrl", 1, 2, 0),
+	FFACTOR(0, "ffac_topc_bus0_pll_div4",
+			"ffac_topc_bus0_pll_div2", 1, 2, 0),
+	FFACTOR(0, "ffac_topc_bus1_pll_div2",
+			"mout_bus1_pll_ctrl", 1, 2, 0),
+	FFACTOR(0, "ffac_topc_cc_pll_div2",
+			"mout_cc_pll_ctrl", 1, 2, 0),
+	FFACTOR(0, "ffac_topc_mfc_pll_div2",
+			"mout_mfc_pll_ctrl", 1, 2, 0),
+};
+
+/* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_aud_pll_ctrl_p)	= { "fin_pll", "fout_aud_pll" };
+PNAME(mout_bus0_pll_ctrl_p)	= { "fin_pll", "fout_bus0_pll" };
+PNAME(mout_bus1_pll_ctrl_p)	= { "fin_pll", "fout_bus1_pll" };
+PNAME(mout_cc_pll_ctrl_p)	= { "fin_pll", "fout_cc_pll" };
+PNAME(mout_mfc_pll_ctrl_p)	= { "fin_pll", "fout_mfc_pll" };
+
+PNAME(mout_topc_group1)	= { "mout_bus0_pll_ctrl", "ffac_topc_bus0_pll_div2",
+	 "mout_bus1_pll_ctrl", "mout_cc_pll" };
+PNAME(mout_topc_group2)	= { "mout_sclk_bus0_pll_cmuc",
+	"mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
+	"mout_sclk_mfc_pll_cmuc" };
+
+PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
+	"ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
+PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
+	"ffac_topc_bus1_pll_div2"};
+PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
+	"ffac_topc_cc_pll_div2"};
+PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
+	"ffac_topc_mfc_pll_div2"};
+
+PNAME(mout_sclk_bus0_pll_out_p)	= {"mout_bus0_pll_ctrl",
+	"ffac_topc_bus0_pll_div2"};
+PNAME(mout_sclk_cmu_apbif_p)	= {"fin_pll", "dout_sclk_cmu_apbif"};
+
+static unsigned long topc_clk_regs[] __initdata = {
+	CC_PLL_LOCK,
+	BUS0_PLL_LOCK,
+	BUS1_DPLL_LOCK,
+	MFC_PLL_LOCK,
+	AUD_PLL_LOCK,
+	MIF_PLL_LOCK,
+	CC_PLL_CON0,
+	CC_PLL_CON1,
+	BUS0_PLL_CON0,
+	BUS0_PLL_CON1,
+	BUS1_DPLL_CON0,
+	BUS1_DPLL_CON1,
+	MFC_PLL_CON0,
+	MFC_PPL_CON1,
+	AUD_PLL_CON0,
+	AUD_PLL_CON1,
+	AUD_PLL_CON2,
+	MIF_PLL_CON0,
+	MIF_PLL_CON1,
+	MIF_PLL_CON2,
+	MUX_SEL_TOPC0,
+	MUX_SEL_TOPC1,
+	MUX_SEL_TOPC2,
+	MUX_SEL_TOPC3,
+	MUX_SEL_TOPC4,
+	MUX_SEL_TOPC5,
+	DIV_TOPC0,
+	DIV_TOPC1,
+	DIV_TOPC2,
+	DIV_TOPC3,
+	DIV_TOPC3,
+	ENABLE_ACLK_TOPC0,
+	ENABLE_ACLK_TOPC1,
+	ENABLE_ACLK_TOPC2,
+	ENABLE_SCLK_TOPC0,
+	ENABLE_SCLK_TOPC1,
+};
+
+static struct samsung_mux_clock topc_mux_clks[] __initdata = {
+	/* Check TOPC TOP0 and TOP1 clocks again*/
+	MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
+	MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
+	MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
+	MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
+
+	MUX(0, "mout_sclk_bus0_pll_cmuc",
+			mout_sclk_bus0_pll_cmuc_p, MUX_SEL_TOPC0, 16, 2),
+	MUX(0, "mout_sclk_bus1_pll_cmuc",
+			mout_sclk_bus1_pll_cmuc_p, MUX_SEL_TOPC0, 20, 1),
+	MUX(0, "mout_sclk_cc_pll_cmuc",
+			mout_sclk_cc_pll_cmuc_p, MUX_SEL_TOPC0, 24, 1),
+	MUX(0, "mout_sclk_mfc_pll_cmuc",
+			mout_sclk_mfc_pll_cmuc_p, MUX_SEL_TOPC0, 28, 1),
+
+	MUX(0, "mout_sclk_bus_pll_g3d",
+			mout_topc_group1, MUX_SEL_TOPC1, 20, 2),
+	MUX(0, "mout_sclk_bus0_pll_out",
+			mout_sclk_bus0_pll_out_p, MUX_SEL_TOPC1, 16, 1),
+	MUX(0, "mout_sclk_bus0_pll_mif",
+			mout_topc_group1, MUX_SEL_TOPC1, 12, 2),
+	MUX(0, "mout_sclk_bus0_pll_atlas",
+			mout_topc_group1, MUX_SEL_TOPC1, 4, 2),
+	MUX(0, "mout_aud_pll_ctrl",
+			mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
+
+	MUX(0, "mout_aclk_ccore_532", mout_topc_group2, MUX_SEL_TOPC2, 0, 2),
+	MUX(0, "mout_aclk_ccore_133", mout_topc_group2,	MUX_SEL_TOPC2, 4, 2),
+	MUX(0, "mout_aclk_bus0_532", mout_topc_group2, MUX_SEL_TOPC2, 8, 2),
+	MUX(0, "mout_aclk_bus1_532", mout_topc_group2, MUX_SEL_TOPC2, 12, 2),
+	MUX(0, "mout_aclk_bus1_200", mout_topc_group2, MUX_SEL_TOPC2, 16, 2),
+	MUX(0, "mout_aclk_imem_266", mout_topc_group2, MUX_SEL_TOPC2, 20, 2),
+	MUX(0, "mout_aclk_imem_200", mout_topc_group2, MUX_SEL_TOPC2, 24, 2),
+	MUX(0, "mout_aclk_imem_100", mout_topc_group2, MUX_SEL_TOPC2, 28, 2),
+
+	MUX(0, "mout_aclk_g2d_400", mout_topc_group2, MUX_SEL_TOPC3, 0, 2),
+	MUX(0, "mout_aclk_g2d_266", mout_topc_group2, MUX_SEL_TOPC3, 4, 2),
+	MUX(0, "mout_aclk_mfc_532", mout_topc_group2, MUX_SEL_TOPC3, 8, 2),
+	MUX(0, "mout_aclk_hevc_532", mout_topc_group2, MUX_SEL_TOPC3, 12, 2),
+	MUX(0, "mout_aclk_mfc_bus_532", mout_topc_group2,
+			MUX_SEL_TOPC3, 16, 2),
+	MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
+	MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
+
+	MUX(0, "mout_sclk_cmu_apbif", mout_topc_group2, MUX_SEL_TOPC4, 0, 2),
+	MUX(0, "mout_sclk_cmuc_apbif", mout_sclk_cmu_apbif_p,
+			MUX_SEL_TOPC4, 16, 1),
+};
+
+static struct samsung_div_clock topc_div_clks[] __initdata = {
+	DIV(0, "dout_aclk_ccore_532", "mout_aclk_ccore_532", DIV_TOPC0, 0, 3),
+	DIV(0, "dout_aclk_ccore_133", "mout_aclk_ccore_133", DIV_TOPC0, 4, 4),
+	DIV(0, "dout_aclk_bus0_532", "mout_aclk_bus0_532", DIV_TOPC0, 8, 3),
+	DIV(0, "dout_aclk_bus1_532", "mout_aclk_bus1_532", DIV_TOPC0, 12, 3),
+	DIV(0, "dout_aclk_bus1_200", "mout_aclk_bus1_200", DIV_TOPC0, 16, 3),
+	DIV(0, "dout_aclk_imem_266", "mout_aclk_imem_266", DIV_TOPC0, 20, 3),
+	DIV(0, "dout_aclk_imem_200", "mout_aclk_imem_200", DIV_TOPC0, 24, 3),
+	DIV(0, "dout_aclk_imem_100", "mout_aclk_imem_100", DIV_TOPC0, 28, 3),
+
+	DIV(0, "dout_aclk_g2d_400", "mout_aclk_g2d_400", DIV_TOPC1, 0, 3),
+	DIV(0, "dout_aclk_g2d_266", "mout_aclk_g2d_266", DIV_TOPC1, 4, 3),
+	DIV(0, "dout_aclk_mfc_532", "mout_aclk_mfc_532", DIV_TOPC1, 8, 3),
+	DIV(0, "dout_aclk_hevc_532", "mout_aclk_hevc_532", DIV_TOPC1, 12, 3),
+	DIV(0, "dout_aclk_mfc_bus_532", "mout_aclk_mfc_bus_532",
+			DIV_TOPC1, 16, 3),
+	DIV(0, "dout_aclk_mscl_532", "mout_aclk_mscl_532", DIV_TOPC1, 20, 3),
+	DIV(0, "dout_aclk_peris_66", "mout_aclk_peris_66", DIV_TOPC1, 24, 4),
+
+	DIV(0, "dout_sclk_cmu_apbif", "mout_sclk_cmu_apbif", DIV_TOPC2, 0, 4),
+
+	DIV(0, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out", DIV_TOPC3, 0, 3),
+	DIV(0, "dout_sclk_bus0_pll_mif", "mout_sclk_bus0_pll_mif",
+			DIV_TOPC3, 4, 3),
+	DIV(0, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl", DIV_TOPC3, 8, 3),
+	DIV(0, "dout_sclk_cc_pll", "mout_cc_pll_ctrl", DIV_TOPC3, 12, 3),
+	DIV(0, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl", DIV_TOPC3, 16, 3),
+	DIV(0, "dout_sclk_bus_pll_g3d", "mout_sclk_bus_pll_g3d",
+			DIV_TOPC3, 20, 3),
+	DIV(0, "dout_sclk_aud_pll", "mout_aud_pll_ctrl", DIV_TOPC3, 28, 3),
+};
+
+static struct samsung_gate_clock topc_gate_clks[] __initdata = {
+	GATE(ACLK_CCORE_532, "aclk_ccore_532", "dout_aclk_ccore_532",
+		ENABLE_ACLK_TOPC0, 0, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
+		ENABLE_ACLK_TOPC0, 4, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_BUS0_532, "aclk_bus0_532", "dout_aclk_bus0_532",
+		ENABLE_ACLK_TOPC0, 8, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_BUS1_532, "aclk_bus1_532", "dout_aclk_bus1_532",
+		ENABLE_ACLK_TOPC0, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_BUS1_200, "aclk_bus1_200", "dout_aclk_bus1_200",
+		ENABLE_ACLK_TOPC0, 16, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_IMEM_266, "aclk_imem_266", "dout_aclk_imem_266",
+		ENABLE_ACLK_TOPC0, 20, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_IMEM_200, "aclk_imem_200", "dout_aclk_imem_200",
+		ENABLE_ACLK_TOPC0, 24, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_IMEM_100, "aclk_imem_100", "dout_aclk_imem_100",
+		ENABLE_ACLK_TOPC0, 28, CLK_IGNORE_UNUSED, 0),
+
+	GATE(ACLK_G2D_400, "aclk_g2d_400", "dout_aclk_g2d_400",
+		ENABLE_ACLK_TOPC1, 0, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_G2D_266, "aclk_g2d_266", "dout_aclk_g2d_266",
+		ENABLE_ACLK_TOPC1, 4, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_MFC_532, "aclk_mfc_532", "dout_aclk_mfc_532",
+		ENABLE_ACLK_TOPC1, 8, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_HEVC_532, "aclk_hevc_532", "dout_aclk_hevc_532",
+		ENABLE_ACLK_TOPC1, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_MFC_BUS_532, "aclk_mfc_bus_532", "dout_aclk_mfc_bus_532",
+		ENABLE_ACLK_TOPC1, 16, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
+		ENABLE_ACLK_TOPC1, 20, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
+		ENABLE_ACLK_TOPC1, 24, CLK_IGNORE_UNUSED, 0),
+
+	GATE(SCLK_CMU_APBIF, "sclk_cmu_apbif", "dout_sclk_cmu_apbif",
+		ENABLE_SCLK_TOPC0, 0, CLK_IGNORE_UNUSED, 0),
+
+	GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
+		ENABLE_SCLK_TOPC1, 0, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
+		ENABLE_SCLK_TOPC1, 1, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
+		ENABLE_SCLK_TOPC1, 4, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
+		ENABLE_SCLK_TOPC1, 5, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_BUS0_PLL_MIF, "sclk_bus0_pll_mif", "dout_sclk_bus0_pll_mif",
+		ENABLE_SCLK_TOPC1, 6, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_BUS0_PLL_ATLAS, "sclk_bus0_pll_atlas",
+		"dout_sclk_bus0_pll_atlas",
+		ENABLE_SCLK_TOPC1, 7, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_BUS_PLL_G3D, "sclk_bus_pll_g3d", "dout_sclk_bus_pll_g3d",
+		ENABLE_SCLK_TOPC1, 9, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
+		ENABLE_SCLK_TOPC1, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
+		ENABLE_SCLK_TOPC1, 13, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
+		ENABLE_SCLK_TOPC1, 16, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
+		ENABLE_SCLK_TOPC1, 17, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
+		ENABLE_SCLK_TOPC1, 20, CLK_IGNORE_UNUSED, 0),
+};
+
+static struct samsung_pll_clock topc_pll_clks[] __initdata = {
+	PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll",
+		BUS0_PLL_LOCK, BUS0_PLL_CON0,
+		pll1451x_24mhz_tbl),
+	PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll",
+		CC_PLL_LOCK, CC_PLL_CON0,
+		pll1452x_24mhz_tbl),
+	PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll",
+		BUS1_DPLL_LOCK, BUS1_DPLL_CON0,
+		pll1452x_24mhz_tbl),
+	PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll",
+		MFC_PLL_LOCK, MFC_PLL_CON0,
+		pll1452x_24mhz_tbl),
+	PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll",
+		AUD_PLL_LOCK, AUD_PLL_CON0,
+		pll1460x_24mhz_tbl),
+};
+
+static void __init exynos7_clk_topc_init(struct device_node *np)
+{
+	struct exynos_cmu_info cmu = {0};
+
+	cmu.pll_clks = topc_pll_clks;
+	cmu.nr_pll_clks = ARRAY_SIZE(topc_pll_clks);
+	cmu.mux_clks = topc_mux_clks;
+	cmu.nr_mux_clks = ARRAY_SIZE(topc_mux_clks);
+	cmu.div_clks = topc_div_clks;
+	cmu.nr_div_clks = ARRAY_SIZE(topc_div_clks);
+	cmu.gate_clks = topc_gate_clks;
+	cmu.nr_gate_clks = ARRAY_SIZE(topc_gate_clks);
+	cmu.fixed_factor_clks = topc_fixed_factor_clks;
+	cmu.nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks);
+	cmu.nr_clk_ids = TOPC_NR_CLK;
+	cmu.clk_regs = topc_clk_regs;
+	cmu.nr_clk_regs = ARRAY_SIZE(topc_clk_regs);
+
+	exynos_cmu_register_one(np, &cmu);
+}
+
+CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
+		exynos7_clk_topc_init);
+
+/* Register Offset definitions for CMU_TOP0 (0x105D0000) */
+#define	MUX_SEL_TOP00			0x0200
+#define	MUX_SEL_TOP01			0x0204
+#define	MUX_SEL_TOP03			0x020C
+#define	MUX_SEL_TOP04			0x0210
+#define	MUX_SEL_TOP05			0x0214
+#define	MUX_SEL_TOP06			0x0218
+#define	MUX_SEL_TOP07			0x021C
+#define	MUX_SEL_TOP0_DISP		0x0220
+#define	MUX_SEL_TOP0_PERIC0		0x0230
+#define	MUX_SEL_TOP0_PERIC1		0x0234
+#define	MUX_SEL_TOP0_PERIC2		0x0238
+#define	MUX_SEL_TOP0_PERIC3		0x023C
+#define	DIV_TOP03			0x060C
+#define	DIV_TOP04			0x0610
+#define	DIV_TOP05			0x0614
+#define	DIV_TOP06			0x0618
+#define	DIV_TOP07			0x061C
+#define	DIV_TOP0_DISP			0x0620
+#define	DIV_TOP0_PERIC0			0x0630
+#define	DIV_TOP0_PERIC1			0x0634
+#define	DIV_TOP0_PERIC2			0x0638
+#define	DIV_TOP0_PERIC3			0x063C
+#define	ENABLE_ACLK_TOP02		0x0808
+#define	ENABLE_ACLK_TOP03		0x080C
+#define	ENABLE_ACLK_TOP04		0x0810
+#define	ENABLE_ACLK_TOP05		0x0814
+#define	ENABLE_ACLK_TOP06		0x0818
+#define	ENABLE_ACLK_TOP07		0x081C
+#define	ENABLE_SCLK_TOP0_DISP		0x0A20
+#define	ENABLE_SCLK_TOP0_PERIC0		0x0A30
+#define	ENABLE_SCLK_TOP0_PERIC1		0x0A34
+#define	ENABLE_SCLK_TOP0_PERIC2		0x0A38
+#define	ENABLE_SCLK_TOP0_PERIC3		0x0A3C
+
+/* List of parent clocks for Muxes in CMU_TOP0 */
+PNAME(mout_bus0_pll_p)	= { "fin_pll", "sclk_bus0_pll_a" };
+PNAME(mout_bus1_pll_p)	= { "fin_pll", "sclk_bus1_pll_a" };
+PNAME(mout_cc_pll_p)	= { "fin_pll", "sclk_cc_pll_a" };
+PNAME(mout_mfc_pll_p)	= { "fin_pll", "sclk_mfc_pll_a" };
+
+PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
+	"ffac_top0_bus0_pll_div2"};
+PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll",
+	"ffac_top0_bus1_pll_div2"};
+PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll",
+	"ffac_top0_cc_pll_div2"};
+PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
+	"ffac_top0_mfc_pll_div2"};
+
+PNAME(mout_top0_aud_pll_p)	= {"fin_pll", "sclk_aud_pll"};
+
+PNAME(mout_sclk_cmu0_apbif_p)	= {"fin_pll", "sclk_cmu_apbif"};
+
+PNAME(mout_top0_group1)	= {"mout_top0_half_bus0_pll",
+	"mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
+	"mout_top0_half_mfc_pll"};
+PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
+	"ioclk_audiocdclk1", "ioclk_spdif_extclk",
+	"mout_top0_aud_pll",	"mout_top0_half_bus0_pll",
+	"mout_top0_half_bus1_pll"};
+PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll",
+	"mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"};
+
+static unsigned long top0_clk_regs[] __initdata = {
+	MUX_SEL_TOP00,
+	MUX_SEL_TOP01,
+	MUX_SEL_TOP03,
+	MUX_SEL_TOP04,
+	MUX_SEL_TOP05,
+	MUX_SEL_TOP06,
+	MUX_SEL_TOP07,
+	MUX_SEL_TOP0_DISP,
+	MUX_SEL_TOP0_PERIC0,
+	MUX_SEL_TOP0_PERIC1,
+	MUX_SEL_TOP0_PERIC2,
+	MUX_SEL_TOP0_PERIC3,
+	DIV_TOP03,
+	DIV_TOP04,
+	DIV_TOP05,
+	DIV_TOP06,
+	DIV_TOP07,
+	DIV_TOP0_DISP,
+	DIV_TOP0_PERIC0,
+	DIV_TOP0_PERIC1,
+	DIV_TOP0_PERIC2,
+	DIV_TOP0_PERIC3,
+	ENABLE_ACLK_TOP02,
+	ENABLE_ACLK_TOP03,
+	ENABLE_ACLK_TOP04,
+	ENABLE_ACLK_TOP05,
+	ENABLE_ACLK_TOP06,
+	ENABLE_ACLK_TOP07,
+	ENABLE_SCLK_TOP0_DISP,
+	ENABLE_SCLK_TOP0_PERIC0,
+	ENABLE_SCLK_TOP0_PERIC1,
+	ENABLE_SCLK_TOP0_PERIC2,
+	ENABLE_SCLK_TOP0_PERIC3,
+};
+
+static struct samsung_mux_clock top0_mux_clks[] __initdata = {
+	MUX(0, "mout_top0_aud_pll", mout_top0_aud_pll_p, MUX_SEL_TOP00, 0, 1),
+	MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
+	MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
+	MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
+	MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1),
+
+	MUX(0, "mout_top0_half_mfc_pll",
+			mout_top0_half_mfc_pll_p, MUX_SEL_TOP01, 4, 1),
+	MUX(0, "mout_top0_half_cc_pll",
+			mout_top0_half_cc_pll_p, MUX_SEL_TOP01, 8, 1),
+	MUX(0, "mout_top0_half_bus1_pll",
+			mout_top0_half_bus1_pll_p, MUX_SEL_TOP01, 12, 1),
+	MUX(0, "mout_top0_half_bus0_pll",
+			mout_top0_half_bus0_pll_p, MUX_SEL_TOP01, 16, 1),
+	MUX(0, "mout_sclk_cmu0_apbif",
+			mout_sclk_cmu0_apbif_p, MUX_SEL_TOP01, 28, 1),
+
+	MUX(0, "mout_aclk_vpp1_400", mout_top0_group1, MUX_SEL_TOP03, 4, 2),
+	MUX(0, "mout_aclk_vpp0_400", mout_top0_group1, MUX_SEL_TOP03, 8, 2),
+	MUX(0, "mout_aclk_peric1_66", mout_top0_group1,	MUX_SEL_TOP03, 12, 2),
+	MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
+	MUX(0, "mout_aclk_disp_400", mout_top0_group1, MUX_SEL_TOP03, 28, 2),
+	/* top0 block for disp */
+	MUX(0, "mout_sclk_hdmi_spdif", mout_top0_group3,
+			MUX_SEL_TOP0_DISP, 12, 3),
+	MUX(0, "mout_sclk_dsd", mout_top0_group1,
+			MUX_SEL_TOP0_DISP, 16, 2),
+	MUX(0, "mout_sclk_decon_vclk", mout_top0_group1,
+			MUX_SEL_TOP0_DISP, 20, 2),
+	MUX(0, "mout_sclk_decon_ext_eclk",
+			mout_top0_group1, MUX_SEL_TOP0_DISP, 24, 2),
+	MUX(0, "mout_sclk_decon_int_eclk",
+			mout_top0_group1, MUX_SEL_TOP0_DISP, 28, 2),
+	/* top0 block for peric */
+	MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
+	MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
+	MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
+
+	MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
+	MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
+
+	MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
+	MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
+
+	MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
+	MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
+	MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
+	MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
+	MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
+};
+
+static struct samsung_div_clock top0_div_clks[] __initdata = {
+	DIV(0, "dout_aclk_peric1_66", "mout_aclk_peric1_66", DIV_TOP03, 12, 6),
+	DIV(0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", DIV_TOP03, 20, 6),
+	DIV(0, "dout_aclk_disp_400", "mout_aclk_disp_400", DIV_TOP03, 28, 4),
+
+	DIV(0, "dout_sclk_hdmi_spdif",
+			"mout_sclk_hdmi_spdif", DIV_TOP0_DISP, 12, 4),
+	DIV(0, "dout_sclk_dsd", "mout_sclk_dsd", DIV_TOP0_DISP, 16, 4),
+	DIV(0, "dout_sclk_decon_vclk",
+			"mout_sclk_decon_vclk", DIV_TOP0_DISP, 20, 4),
+	DIV(0, "dout_sclk_decon_ext_eclk",
+			"mout_sclk_decon_ext_eclk", DIV_TOP0_DISP, 24, 4),
+	DIV(0, "dout_sclk_decon_int_eclk",
+			"mout_sclk_decon_int_eclk", DIV_TOP0_DISP, 28, 4),
+
+	DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
+	DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
+	DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
+
+	DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
+	DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
+
+	DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
+	DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
+
+	DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
+	DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
+	DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
+	DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
+	DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
+};
+
+static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+	GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
+			ENABLE_ACLK_TOP03, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
+			ENABLE_ACLK_TOP03, 20, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_ACLK_DISP_400, "aclk_disp_400", "dout_aclk_disp_400",
+			ENABLE_ACLK_TOP03, 28, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "dout_sclk_hdmi_spdif",
+			ENABLE_SCLK_TOP0_DISP, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_DSD, "sclk_dsd", "dout_sclk_dsd",
+			ENABLE_SCLK_TOP0_DISP, 16, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk", "dout_sclk_decon_vclk",
+			ENABLE_SCLK_TOP0_DISP, 20, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_DECON_EXT_ECLK, "sclk_decon_ext_eclk",
+			"dout_sclk_decon_ext_eclk",
+			ENABLE_SCLK_TOP0_DISP, 24, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_DECON_INT_ECLK, "sclk_decon_int_eclk",
+			"dout_sclk_decon_int_eclk",
+			ENABLE_SCLK_TOP0_DISP, 28, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
+			ENABLE_SCLK_TOP0_PERIC0, 4, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
+			ENABLE_SCLK_TOP0_PERIC0, 8, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
+			ENABLE_SCLK_TOP0_PERIC0, 20, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
+			ENABLE_SCLK_TOP0_PERIC1, 8, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
+			ENABLE_SCLK_TOP0_PERIC1, 20, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
+			ENABLE_SCLK_TOP0_PERIC2, 8, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
+			ENABLE_SCLK_TOP0_PERIC2, 20, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
+			ENABLE_SCLK_TOP0_PERIC3, 4, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
+			ENABLE_SCLK_TOP0_PERIC3, 8, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
+			ENABLE_SCLK_TOP0_PERIC3, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
+			ENABLE_SCLK_TOP0_PERIC3, 16, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
+			ENABLE_SCLK_TOP0_PERIC3, 20, CLK_IGNORE_UNUSED, 0),
+};
+
+static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
+	FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0),
+};
+
+static void __init exynos7_clk_top0_init(struct device_node *np)
+{
+	struct exynos_cmu_info cmu = {0};
+
+	cmu.mux_clks = top0_mux_clks;
+	cmu.nr_mux_clks = ARRAY_SIZE(top0_mux_clks);
+	cmu.div_clks = top0_div_clks;
+	cmu.nr_div_clks = ARRAY_SIZE(top0_div_clks);
+	cmu.gate_clks = top0_gate_clks;
+	cmu.nr_gate_clks = ARRAY_SIZE(top0_gate_clks);
+	cmu.fixed_factor_clks = top0_fixed_factor_clks;
+	cmu.nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks);
+	cmu.nr_clk_ids = TOP0_NR_CLK;
+	cmu.clk_regs = top0_clk_regs;
+	cmu.nr_clk_regs = ARRAY_SIZE(top0_clk_regs);
+
+	exynos_cmu_register_one(np, &cmu);
+}
+
+CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
+		exynos7_clk_top0_init);
+
+/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
+#define	MUX_SEL_TOP10			0x0200
+#define	MUX_SEL_TOP11			0x0204
+#define	MUX_SEL_TOP13			0x020C
+#define	MUX_SEL_TOP1_FSYS0		0x0224
+#define	MUX_SEL_TOP1_FSYS1		0x0228
+#define	MUX_SEL_TOP1_FSYS11		0x022C
+#define	DIV_TOP13			0x060C
+#define	DIV_TOP1_FSYS0			0x0624
+#define	DIV_TOP1_FSYS1			0x0628
+#define	DIV_TOP1_FSYS11			0x062C
+#define	ENABLE_ACLK_TOP12		0x0808
+#define	ENABLE_ACLK_TOP13		0x080C
+#define	ENABLE_SCLK_TOP1_FSYS0		0x0A24
+#define	ENABLE_SCLK_TOP1_FSYS1		0x0A28
+#define	ENABLE_SCLK_TOP1_FSYS11		0x0A2C
+
+/* List of parent clocks for Muxes in CMU_TOP1 */
+PNAME(mout_top1_bus0_pll_p)	= { "fin_pll", "sclk_bus0_pll_b" };
+PNAME(mout_top1_bus1_pll_p)	= { "fin_pll", "sclk_bus1_pll_b" };
+PNAME(mout_top1_cc_pll_p)	= { "fin_pll", "sclk_cc_pll_b" };
+PNAME(mout_top1_mfc_pll_p)	= { "fin_pll", "sclk_mfc_pll_b" };
+
+PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
+	"ffac_top1_bus0_pll_div2"};
+PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
+	"ffac_top1_bus1_pll_div2"};
+PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
+	"ffac_top1_cc_pll_div2"};
+PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
+	"ffac_top1_mfc_pll_div2"};
+
+PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
+	"mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
+	"mout_top1_half_mfc_pll"};
+
+PNAME(mout_sclk_cmu1_apbif_p)	= {"fin_pll", "sclk_cmu_apbif"};
+
+static unsigned long top1_clk_regs[] __initdata = {
+	MUX_SEL_TOP10,
+	MUX_SEL_TOP11,
+	MUX_SEL_TOP13,
+	MUX_SEL_TOP1_FSYS0,
+	MUX_SEL_TOP1_FSYS1,
+	MUX_SEL_TOP1_FSYS11,
+	DIV_TOP13,
+	DIV_TOP0_DISP,
+	DIV_TOP1_FSYS0,
+	DIV_TOP1_FSYS1,
+	DIV_TOP1_FSYS11,
+	ENABLE_ACLK_TOP12,
+	ENABLE_ACLK_TOP13,
+	ENABLE_SCLK_TOP1_FSYS0,
+	ENABLE_SCLK_TOP1_FSYS1,
+	ENABLE_SCLK_TOP1_FSYS11,
+};
+
+static struct samsung_mux_clock top1_mux_clks[] __initdata = {
+	MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
+	MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
+	MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
+			MUX_SEL_TOP10, 12, 1),
+	MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
+			MUX_SEL_TOP10, 16, 1),
+
+	MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
+			MUX_SEL_TOP11, 4, 1),
+	MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
+			MUX_SEL_TOP11, 8, 1),
+	MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
+			MUX_SEL_TOP11, 12, 1),
+	MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
+			MUX_SEL_TOP11, 16, 1),
+	MUX(0, "mout_sclk_cmu1_apbif", mout_sclk_cmu1_apbif_p,
+			MUX_SEL_TOP11, 28, 1),
+
+	MUX(0, "mout_aclk_fsys1_200", mout_top1_group1,
+			MUX_SEL_TOP13, 24, 2),
+	MUX(0, "mout_aclk_fsys0_200", mout_top1_group1,
+			MUX_SEL_TOP13, 28, 2),
+
+	/* top1 block for fsys */
+	MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
+			MUX_SEL_TOP1_FSYS0, 0, 2),
+	MUX(0, "mout_sclk_phy_fsys0", mout_top1_group1,
+			MUX_SEL_TOP1_FSYS0, 8, 2),
+	MUX(0, "mout_sclk_ufsunipro11", mout_top1_group1,
+			MUX_SEL_TOP1_FSYS0, 16, 2),
+	MUX(0, "mout_sclk_mmc2", mout_top1_group1,
+			MUX_SEL_TOP1_FSYS0, 24, 2),
+	MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
+			MUX_SEL_TOP1_FSYS0, 28, 2),
+
+	MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
+			MUX_SEL_TOP1_FSYS1, 0, 2),
+	MUX(0, "mout_sclk_tlx400_wifi1", mout_top1_group1,
+			MUX_SEL_TOP1_FSYS1, 8, 2),
+	MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
+			MUX_SEL_TOP1_FSYS1, 16, 2),
+	MUX(0, "mout_sclk_mmc1", mout_top1_group1,
+			MUX_SEL_TOP1_FSYS1, 24, 2),
+	MUX(0, "mout_sclk_mmc0", mout_top1_group1,
+			MUX_SEL_TOP1_FSYS1, 28, 2),
+
+	MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
+			MUX_SEL_TOP1_FSYS11, 24, 2),
+};
+
+static struct samsung_div_clock top1_div_clks[] __initdata = {
+	DIV(0, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", DIV_TOP13, 24, 4),
+	DIV(0, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", DIV_TOP13, 28, 4),
+
+	/* top1 block for fsys */
+	DIV(0, "dout_sclk_phy_fsys0_26m", "mout_sclk_phy_fsys0_26m",
+			DIV_TOP1_FSYS0, 0, 6),
+	DIV(0, "dout_sclk_phy_fsys0", "mout_sclk_phy_fsys0",
+			DIV_TOP1_FSYS0, 8, 6),
+	DIV(0, "dout_sclk_ufsunipro11", "mout_sclk_ufsunipro11",
+			DIV_TOP1_FSYS0, 16, 6),
+	DIV(0, "dout_sclk_mmc2", "mout_sclk_mmc2",
+			DIV_TOP1_FSYS0, 24, 4),
+	DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
+			DIV_TOP1_FSYS0, 28, 4),
+
+	DIV(0, "dout_sclk_phy_fsys1", "mout_sclk_phy_fsys1",
+			DIV_TOP1_FSYS1, 0, 6),
+	DIV(0, "dout_sclk_tlx400_wifi1", "mout_sclk_tlx400_wifi1",
+			DIV_TOP1_FSYS1, 8, 6),
+	DIV(0, "dout_sclk_ufsunipro20", "mout_sclk_ufsunipro20",
+			DIV_TOP1_FSYS1, 16, 6),
+	DIV(0, "dout_sclk_mmc1", "mout_sclk_mmc1", DIV_TOP1_FSYS1, 24, 4),
+	DIV(0, "dout_sclk_mmc0", "mout_sclk_mmc0", DIV_TOP1_FSYS1, 28, 4),
+
+	DIV(0, "dout_sclk_phy_fsys1_26m", "mout_sclk_phy_fsys1_26m",
+			DIV_TOP1_FSYS11, 24, 6),
+};
+
+static struct samsung_gate_clock top1_gate_clks[] __initdata = {
+	GATE(ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
+			ENABLE_ACLK_TOP13, 24, CLK_IGNORE_UNUSED, 0),
+	GATE(ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
+			ENABLE_ACLK_TOP13, 28, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_SCLK_PHY_FSYS0_26M, "sclk_phy_fsys0_26m",
+			"dout_sclk_phy_fsys0_26m",
+			ENABLE_SCLK_TOP1_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_PHY_FSYS0, "sclk_phy_fsys0", "dout_sclk_phy_fsys0",
+			ENABLE_SCLK_TOP1_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_UFSUNIPRO11, "sclk_ufsunipro11",
+			"dout_sclk_ufsunipro11",
+			ENABLE_SCLK_TOP1_FSYS0, 16, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
+			ENABLE_SCLK_TOP1_FSYS0, 24, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_USBDRD300, "sclk_usbdrd300", "dout_sclk_usbdrd300",
+			ENABLE_SCLK_TOP1_FSYS0, 28, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1",
+			ENABLE_SCLK_TOP1_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_TLX400_WIFI1, "sclk_tlx400_wifi1",
+			"dout_sclk_tlx400_wifi1",
+			ENABLE_SCLK_TOP1_FSYS1, 8, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20",
+			"dout_sclk_ufsunipro20",
+			ENABLE_SCLK_TOP1_FSYS1, 16, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
+			ENABLE_SCLK_TOP1_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
+			ENABLE_SCLK_TOP1_FSYS1, 28, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m",
+			"dout_sclk_phy_fsys1_26m",
+			ENABLE_SCLK_TOP1_FSYS11, 24, CLK_IGNORE_UNUSED, 0),
+};
+
+static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
+	FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
+};
+
+static void __init exynos7_clk_top1_init(struct device_node *np)
+{
+	struct exynos_cmu_info cmu = {0};
+
+	cmu.mux_clks = top1_mux_clks;
+	cmu.nr_mux_clks = ARRAY_SIZE(top1_mux_clks);
+	cmu.div_clks = top1_div_clks;
+	cmu.nr_div_clks = ARRAY_SIZE(top1_div_clks);
+	cmu.gate_clks = top1_gate_clks;
+	cmu.nr_gate_clks = ARRAY_SIZE(top1_gate_clks);
+	cmu.fixed_factor_clks = top1_fixed_factor_clks;
+	cmu.nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks);
+	cmu.nr_clk_ids = TOP1_NR_CLK;
+	cmu.clk_regs = top1_clk_regs;
+	cmu.nr_clk_regs = ARRAY_SIZE(top1_clk_regs);
+
+	exynos_cmu_register_one(np, &cmu);
+}
+
+CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
+		exynos7_clk_top1_init);
+
+/* Register Offset definitions for CMU_CCORE (0x105B0000) */
+#define	MUX_SEL_CCORE			0x0200
+#define	DIV_CCORE			0x0600
+#define	ENABLE_ACLK_CCORE0		0x0800
+#define	ENABLE_ACLK_CCORE1		0x0804
+#define	ENABLE_PCLK_CCORE		0x0900
+
+/*
+ * List of parent clocks for Muxes in CMU_CCORE
+ */
+PNAME(mout_aclk_ccore_532_p)	= { "fin_pll", "aclk_ccore_532" };
+PNAME(mout_aclk_ccore_133_p)	= { "fin_pll", "aclk_ccore_133" };
+
+static unsigned long ccore_clk_regs[] __initdata = {
+	MUX_SEL_CCORE,
+	DIV_CCORE,
+	ENABLE_ACLK_CCORE0,
+	ENABLE_ACLK_CCORE1,
+	ENABLE_PCLK_CCORE,
+};
+
+static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
+	MUX(0, "mout_aclk_ccore_532_user",
+			mout_aclk_ccore_532_p,
+			MUX_SEL_CCORE, 0, 1),
+	MUX(0, "mout_aclk_ccore_133_user",
+			mout_aclk_ccore_133_p,
+			MUX_SEL_CCORE, 1, 1),
+};
+
+struct samsung_div_clock ccore_div_clks[] __initdata = {
+	DIV(0, "dout_aclk_ccore_266", "mout_aclk_ccore_532_user",
+			DIV_CCORE, 0, 3),
+};
+
+static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
+	GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
+			ENABLE_PCLK_CCORE, 8, 0, 0),
+};
+
+static void __init exynos7_clk_ccore_init(struct device_node *np)
+{
+	struct exynos_cmu_info cmu = {0};
+
+	cmu.mux_clks = ccore_mux_clks;
+	cmu.nr_mux_clks = ARRAY_SIZE(ccore_mux_clks);
+	cmu.div_clks = ccore_div_clks;
+	cmu.nr_div_clks = ARRAY_SIZE(ccore_div_clks);
+	cmu.gate_clks = ccore_gate_clks;
+	cmu.nr_gate_clks = ARRAY_SIZE(ccore_gate_clks);
+	cmu.nr_clk_ids = CCORE_NR_CLK;
+	cmu.clk_regs = ccore_clk_regs;
+	cmu.nr_clk_regs = ARRAY_SIZE(ccore_clk_regs);
+
+	exynos_cmu_register_one(np, &cmu);
+}
+
+CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
+		exynos7_clk_ccore_init);
+
+/* Register Offset definitions for CMU_PERIC0 (0x13610000) */
+#define	MUX_SEL_PERIC0			0x0200
+#define	ENABLE_PCLK_PERIC0		0x0900
+#define	ENABLE_SCLK_PERIC0		0x0A00
+
+/* List of parent clocks for Muxes in CMU_PERIC0 */
+PNAME(mout_aclk_peric0_66_p)	= { "fin_pll", "aclk_peric0_66" };
+PNAME(mout_sclk_uart0_p)	= { "fin_pll", "sclk_uart0" };
+
+static unsigned long peric0_clk_regs[] __initdata = {
+	MUX_SEL_PERIC0,
+	ENABLE_PCLK_PERIC0,
+	ENABLE_SCLK_PERIC0,
+};
+
+static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
+	MUX(0, "mout_aclk_peric0_66_user",
+			mout_aclk_peric0_66_p, MUX_SEL_PERIC0, 0, 1),
+	MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
+			MUX_SEL_PERIC0, 16, 1),
+};
+
+static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
+	GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
+			ENABLE_PCLK_PERIC0, 8, CLK_IGNORE_UNUSED, 0),
+	GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
+			ENABLE_PCLK_PERIC0, 9, CLK_IGNORE_UNUSED, 0),
+	GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
+			ENABLE_PCLK_PERIC0, 10, CLK_IGNORE_UNUSED, 0),
+	GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
+			ENABLE_PCLK_PERIC0, 11, CLK_IGNORE_UNUSED, 0),
+	GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
+			ENABLE_PCLK_PERIC0, 12, CLK_IGNORE_UNUSED, 0),
+	GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
+			ENABLE_PCLK_PERIC0, 13, CLK_IGNORE_UNUSED, 0),
+	GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
+			ENABLE_PCLK_PERIC0, 14, CLK_IGNORE_UNUSED, 0),
+	GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
+			ENABLE_PCLK_PERIC0, 16, CLK_IGNORE_UNUSED, 0),
+	GATE(PCLK_ADCIF, "plk_adcif", "mout_aclk_peric0_66_user",
+			ENABLE_PCLK_PERIC0, 20, CLK_IGNORE_UNUSED, 0),
+	GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
+			ENABLE_PCLK_PERIC0, 21, CLK_IGNORE_UNUSED, 0),
+
+	GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
+			ENABLE_SCLK_PERIC0, 16, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_PWM, "sclk_pwm", "fin_pll",
+			ENABLE_SCLK_PERIC0, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static void __init exynos7_clk_peric0_init(struct device_node *np)
+{
+	struct exynos_cmu_info cmu = {0};
+
+	cmu.mux_clks = peric0_mux_clks;
+	cmu.nr_mux_clks = ARRAY_SIZE(peric0_mux_clks);
+	cmu.gate_clks = peric0_gate_clks;
+	cmu.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks);
+	cmu.nr_clk_ids = PERIC0_NR_CLK;
+	cmu.clk_regs = peric0_clk_regs;
+	cmu.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs);
+
+	exynos_cmu_register_one(np, &cmu);
+}
+
+/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
+#define	MUX_SEL_PERIC10			0x0200
+#define	MUX_SEL_PERIC11			0x0204
+#define	ENABLE_PCLK_PERIC1		0x0900
+#define	ENABLE_SCLK_PERIC10		0x0A00
+#define	ENABLE_SCLK_PERIC11		0x0A04
+
+CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
+		exynos7_clk_peric0_init);
+
+/* List of parent clocks for Muxes in CMU_PERIC1 */
+PNAME(mout_aclk_peric1_66_p)	= { "fin_pll", "aclk_peric1_66" };
+PNAME(mout_sclk_uart1_p)	= { "fin_pll", "sclk_uart1" };
+PNAME(mout_sclk_uart2_p)	= { "fin_pll", "sclk_uart2" };
+PNAME(mout_sclk_uart3_p)	= { "fin_pll", "sclk_uart3" };
+PNAME(mout_sclk_spi0_p)		= { "fin_pll", "sclk_spi0" };
+PNAME(mout_sclk_spi1_p)		= { "fin_pll", "sclk_spi1" };
+PNAME(mout_sclk_spi2_p)		= { "fin_pll", "sclk_spi2" };
+PNAME(mout_sclk_spi3_p)		= { "fin_pll", "sclk_spi3" };
+PNAME(mout_sclk_spi4_p)		= { "fin_pll", "sclk_spi4" };
+
+/* fixed rate clocks used in the PERIC1 block */
+struct samsung_fixed_rate_clock fixed_rate_clks_peric1[] __initdata = {
+	FRATE(0, "ioclk_i2s1_bclk", NULL, CLK_IS_ROOT, 25000000),
+	FRATE(0, "ioclk_spi0_clk", NULL, CLK_IS_ROOT, 100000000),
+	FRATE(0, "ioclk_spi1_clk", NULL, CLK_IS_ROOT, 100000000),
+	FRATE(0, "ioclk_spi2_clk", NULL, CLK_IS_ROOT, 100000000),
+	FRATE(0, "ioclk_spi3_clk", NULL, CLK_IS_ROOT, 100000000),
+	FRATE(0, "ioclk_spi4_clk", NULL, CLK_IS_ROOT, 100000000),
+};
+
+static unsigned long peric1_clk_regs[] __initdata = {
+	MUX_SEL_PERIC10,
+	MUX_SEL_PERIC11,
+	ENABLE_PCLK_PERIC1,
+	ENABLE_SCLK_PERIC10,
+	ENABLE_SCLK_PERIC11,
+};
+
+static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
+	MUX(0, "mout_aclk_peric1_66_user",
+		mout_aclk_peric1_66_p, MUX_SEL_PERIC10, 0, 1),
+
+	MUX(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,	MUX_SEL_PERIC11, 0, 1),
+	MUX(0, "mout_sclk_spi1_user", mout_sclk_spi1_p, MUX_SEL_PERIC11, 4, 1),
+	MUX(0, "mout_sclk_spi2_user", mout_sclk_spi2_p, MUX_SEL_PERIC11, 8, 1),
+	MUX(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,	MUX_SEL_PERIC11, 12, 1),
+	MUX(0, "mout_sclk_spi4_user", mout_sclk_spi4_p, MUX_SEL_PERIC11, 16, 1),
+	MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
+			MUX_SEL_PERIC11, 20, 1),
+	MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
+			MUX_SEL_PERIC11, 24, 1),
+	MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
+			MUX_SEL_PERIC11, 28, 1),
+};
+
+static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
+	GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 4, 0, 0),
+	GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 5, 0, 0),
+	GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 6, 0, 0),
+	GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 7, 0, 0),
+	GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 8, 0, 0),
+	GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 9, 0, 0),
+	GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 10, CLK_IGNORE_UNUSED, 0),
+	GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 11, 0, 0),
+	GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 12, 0, 0),
+	GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 13, 0, 0),
+	GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 14, 0, 0),
+	GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 15, 0, 0),
+	GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 16, 0, 0),
+	GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 17, 0, 0),
+	GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 18, 0, 0),
+	GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
+			ENABLE_PCLK_PERIC1, 19, 0, 0),
+
+	GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
+			ENABLE_SCLK_PERIC10, 9, 0, 0),
+	GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
+			ENABLE_SCLK_PERIC10, 10, CLK_IGNORE_UNUSED, 0),
+	GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
+			ENABLE_SCLK_PERIC10, 11, 0, 0),
+	GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
+			ENABLE_SCLK_PERIC10, 12, 0, 0),
+	GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
+			ENABLE_SCLK_PERIC10, 13, 0, 0),
+	GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
+			ENABLE_SCLK_PERIC10, 14, 0, 0),
+	GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
+			ENABLE_SCLK_PERIC10, 15, 0, 0),
+	GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
+			ENABLE_SCLK_PERIC10, 16, 0, 0),
+	GATE(SCLK_I2S1, "sclk_i2s1_user", "dout_sclk_i2s1",
+			ENABLE_SCLK_PERIC10, 17, 0, 0),
+	GATE(SCLK_PCM1, "sclk_pcm1_user", "dout_sclk_pcm1",
+			ENABLE_SCLK_PERIC10, 18, 0, 0),
+	GATE(SCLK_SPDIF, "sclk_spdif_user", "dout_sclk_spdif",
+			ENABLE_SCLK_PERIC10, 19, 0, 0),
+
+	GATE(IOCLK_SPI0_CLK, "ioclk_spi0", "dout_sclk_spi0",
+			ENABLE_SCLK_PERIC11, 12, 0, 0),
+	GATE(IOCLK_SPI1_CLK, "ioclk_spi1", "dout_sclk_spi1",
+			ENABLE_SCLK_PERIC11, 13, 0, 0),
+	GATE(IOCLK_SPI2_CLK, "ioclk_spi2", "dout_sclk_spi2",
+			ENABLE_SCLK_PERIC11, 14, 0, 0),
+	GATE(IOCLK_SPI3_CLK, "ioclk_spi3", "dout_sclk_spi3",
+			ENABLE_SCLK_PERIC11, 15, 0, 0),
+	GATE(IOCLK_SPI4_CLK, "ioclk_spi4", "dout_sclk_spi4",
+			ENABLE_SCLK_PERIC11, 16, 0, 0),
+	GATE(IOCLK_I2S1_BCLK, "ioclk_i2s1", "dout_sclk_i2s1",
+			ENABLE_SCLK_PERIC11, 17, 0, 0),
+};
+
+static void __init exynos7_clk_peric1_init(struct device_node *np)
+{
+	struct exynos_cmu_info cmu = {0};
+
+	cmu.fixed_clks = fixed_rate_clks_peric1;
+	cmu.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_peric1);
+	cmu.mux_clks = peric1_mux_clks;
+	cmu.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks);
+	cmu.gate_clks = peric1_gate_clks;
+	cmu.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks);
+	cmu.nr_clk_ids = PERIC1_NR_CLK;
+	cmu.clk_regs = peric1_clk_regs;
+	cmu.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs);
+
+	exynos_cmu_register_one(np, &cmu);
+}
+
+CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
+		exynos7_clk_peric1_init);
+
+/* Register Offset definitions for CMU_PERIS (0x10040000) */
+#define	MUX_SEL_PERIS			0x0200
+#define	ENABLE_PCLK_PERIS		0x0900
+#define ENABLE_PCLK_PERIS_SECURE_CHIPID	0x0910
+#define	ENABLE_SCLK_PERIS		0x0A00
+#define ENABLE_SCLK_PERIS_SECURE_CHIPID	0x0A10
+
+/* List of parent clocks for Muxes in CMU_PERIS */
+PNAME(mout_aclk_peris_66_p)	= { "fin_pll", "aclk_peris_66" };
+
+static unsigned long peris_clk_regs[] __initdata = {
+	MUX_SEL_PERIS,
+	ENABLE_PCLK_PERIS,
+	ENABLE_SCLK_PERIS,
+	ENABLE_PCLK_PERIS_SECURE_CHIPID,
+	ENABLE_SCLK_PERIS_SECURE_CHIPID,
+};
+
+static struct samsung_mux_clock peris_mux_clks[] __initdata = {
+	MUX(0, "mout_aclk_peris_66_user",
+		mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
+};
+
+static struct samsung_gate_clock peris_gate_clks[] __initdata = {
+	GATE(PCLK_MCT, "pclk_mct", "mout_aclk_peris_66_user",
+			ENABLE_PCLK_PERIS, 5, 0, 0),
+	GATE(PCLK_WDT_ATLAS, "pclk_wdt_atlas", "mout_aclk_peris_66_user",
+			ENABLE_PCLK_PERIS, 6, 0, 0),
+	GATE(PCLK_SYSREG, "pclk_sysreg", "mout_aclk_peris_66_user",
+			ENABLE_PCLK_PERIS, 9, 0, 0),
+	GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
+			ENABLE_PCLK_PERIS, 10, 0, 0),
+
+	GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
+			ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+
+	GATE(SCLK_TMU, "sclk_tmu", "fin_pll",
+			ENABLE_SCLK_PERIS, 10, 0, 0),
+
+	GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
+			ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
+};
+
+static void __init exynos7_clk_peris_init(struct device_node *np)
+{
+	struct exynos_cmu_info cmu = {0};
+
+	cmu.mux_clks = peris_mux_clks;
+	cmu.nr_mux_clks = ARRAY_SIZE(peris_mux_clks);
+	cmu.gate_clks = peris_gate_clks;
+	cmu.nr_gate_clks = ARRAY_SIZE(peris_gate_clks);
+	cmu.nr_clk_ids = PERIS_NR_CLK;
+	cmu.clk_regs = peris_clk_regs;
+	cmu.nr_clk_regs = ARRAY_SIZE(peris_clk_regs);
+
+	exynos_cmu_register_one(np, &cmu);
+}
+
+CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
+		exynos7_clk_peris_init);
+
+/* Register Offset definitions for CMU_BUS0 (0x13400000) */
+#define	MUX_SEL_BUS0			0x0200
+#define	DIV_BUS0			0x0600
+#define	ENABLE_ACLK_BUS0		0x0800
+#define	ENABLE_PCLK_BUS0		0x0900
+
+/* List of parent clocks for Muxes in CMU_BUS0 */
+PNAME(mout_aclk_bus0_532_user_p)	= { "fin_pll", "aclk_bus0_532" };
+
+static unsigned long bus0_clk_regs[] __initdata = {
+	MUX_SEL_BUS0,
+	DIV_BUS0,
+	ENABLE_PCLK_BUS0,
+};
+
+static struct samsung_mux_clock bus0_mux_clks[] __initdata = {
+	MUX(0, "mout_aclk_bus0_532_user",
+		mout_aclk_bus0_532_user_p, MUX_SEL_BUS0, 0, 1),
+};
+
+static struct samsung_div_clock bus0_div_clks[] __initdata = {
+	DIV(0, "dout_pclk_bus0_133", "mout_aclk_bus0_532_user", DIV_BUS0, 0, 3),
+};
+
+static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
+	GATE(ACLK_LH_DISP0, "aclk_lh_disp0", "dout_pclk_bus0_532",
+		ENABLE_ACLK_BUS0, 3, 0, 0),
+	GATE(ACLK_LH_DISP1, "aclk_lh_disp1", "dout_pclk_bus0_532",
+		ENABLE_ACLK_BUS0, 4, 0, 0),
+	GATE(PCLK_GPIO_BUS0, "pclk_gpio_bus0", "dout_pclk_bus0_133",
+		ENABLE_PCLK_BUS0, 13, 0, 0),
+};
+
+static void __init exynos7_clk_bus0_init(struct device_node *np)
+{
+	struct exynos_cmu_info cmu = {0};
+
+	cmu.mux_clks = bus0_mux_clks;
+	cmu.nr_mux_clks = ARRAY_SIZE(bus0_mux_clks);
+	cmu.div_clks = bus0_div_clks;
+	cmu.nr_div_clks = ARRAY_SIZE(bus0_div_clks);
+	cmu.gate_clks = bus0_gate_clks;
+	cmu.nr_gate_clks = ARRAY_SIZE(bus0_gate_clks);
+	cmu.nr_clk_ids = BUS0_NR_CLK;
+	cmu.clk_regs = bus0_clk_regs;
+	cmu.nr_clk_regs = ARRAY_SIZE(bus0_clk_regs);
+
+	exynos_cmu_register_one(np, &cmu);
+}
+
+CLK_OF_DECLARE(exynos7_clk_bus0, "samsung,exynos7-clock-bus0",
+		exynos7_clk_bus0_init);
+
+/* Register Offset definitions for CMU_BUS1 (0x14800000) */
+#define	MUX_SEL_BUS1			0x0200
+#define	DIV_BUS1			0x0600
+#define	ENABLE_ACLK_BUS1		0x0800
+#define	ENABLE_PCLK_BUS1		0x0900
+
+/* List of parent clocks for Muxes in CMU_BUS1 */
+PNAME(mout_aclk_bus1_532_p)	= { "fin_pll", "aclk_bus1_532" };
+PNAME(mout_aclk_bus1_200_p)	= { "fin_pll", "aclk_bus1_200" };
+
+static unsigned long bus1_clk_regs[] __initdata = {
+	MUX_SEL_BUS1,
+	DIV_BUS1,
+	ENABLE_PCLK_BUS1,
+};
+
+static struct samsung_mux_clock bus1_mux_clks[] __initdata = {
+	MUX(0, "mout_aclk_bus1_532_user",
+			mout_aclk_bus1_532_p, MUX_SEL_BUS1, 0, 1),
+	MUX(0, "mout_aclk_bus1_200_user",
+			mout_aclk_bus1_200_p, MUX_SEL_BUS1, 4, 1),
+};
+
+static struct samsung_div_clock bus1_div_clks[] __initdata = {
+	DIV(0, "dout_pclk_bus1_133", "mout_aclk_bus1_532_user", DIV_BUS1, 0, 3),
+};
+
+static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
+	GATE(PCLK_GPIO_BUS1, "pclk_gpio_bus1", "dout_pclk_bus1_133",
+			ENABLE_PCLK_BUS1, 27, 0, 0),
+};
+
+static void __init exynos7_clk_bus1_init(struct device_node *np)
+{
+	struct exynos_cmu_info cmu = {0};
+
+	cmu.mux_clks = bus1_mux_clks;
+	cmu.nr_mux_clks = ARRAY_SIZE(bus1_mux_clks);
+	cmu.div_clks = bus1_div_clks;
+	cmu.nr_div_clks = ARRAY_SIZE(bus1_div_clks);
+	cmu.gate_clks = bus1_gate_clks;
+	cmu.nr_gate_clks = ARRAY_SIZE(bus1_gate_clks);
+	cmu.nr_clk_ids = BUS1_NR_CLK;
+	cmu.clk_regs = bus1_clk_regs;
+	cmu.nr_clk_regs = ARRAY_SIZE(bus1_clk_regs);
+
+	exynos_cmu_register_one(np, &cmu);
+}
+
+CLK_OF_DECLARE(exynos7_clk_bus1, "samsung,exynos7-clock-bus1",
+		exynos7_clk_bus1_init);
+
+/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
+#define	HSIC_PLL_LOCK			0x0000
+#define	HSIC_PLL_CON0			0x0100
+#define	HSIC_PLL_CON1			0x0104
+#define	MUX_SEL_FSYS00			0x0200
+#define	MUX_SEL_FSYS01			0x0204
+#define	MUX_SEL_FSYS02			0x0208
+#define	MUX_SEL_FSYS03			0x020C
+#define	DIV_FSYS0			0x0600
+#define	ENABLE_ACLK_FSYS00		0x0800
+#define	ENABLE_ACLK_FSYS01		0x0804
+#define	ENABLE_PCLK_FSYS0		0x0900
+#define	ENABLE_SCLK_FSYS01		0x0A04
+#define	ENABLE_SCLK_FSYS02		0x0A08
+#define	ENABLE_SCLK_FSYS03		0x0A0C
+#define	ENABLE_SCLK_FSYS04		0x0A10
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS0
+ */
+PNAME(mout_hsic_pll_ctrl_p) = { "fin_pll", "fout_hsic_pll" };
+
+PNAME(mout_aclk_fsys0_200_p)	= { "fin_pll", "aclk_fsys0_200" };
+PNAME(mout_fsys0_group_p)	= { "fin_pll", "fin_pll_26m",
+				"sclk_phy_fsys0_26m" };
+
+PNAME(mout_sclk_usbdrd300_p)	= { "fin_pll", "sclk_usbdrd300" };
+PNAME(mout_sclk_mmc2_p)		= { "fin_pll", "sclk_mmc2" };
+PNAME(mout_sclk_ufsunipro11_p)	= { "fin_pll", "sclk_ufsunipro11" };
+PNAME(mout_sclk_phy_fsys0_p)	= { "fin_pll", "sclk_phy_fsys0" };
+
+
+PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p)	= { "fin_pll",
+				"phyclk_usbdrd300_udrd30_phyclock" };
+PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p)	= { "fin_pll",
+				"phyclk_usbdrd300_udrd30_pipe_pclk" };
+PNAME(mout_phyclk_usbhost20_phy_freeclk_hsic1_p) = { "fin_pll",
+				"phyclk_usbhost20_phy_freeclk_hsic1" };
+PNAME(mout_phyclk_usbhost20_phy_phyclk_hsic1_p)	= { "fin_pll",
+				"phyclk_usbhost20_phy_phyclk_hsic1" };
+
+PNAME(mout_phyclk_ufs_tx0_p) = { "fin_pll", "phyclk_ufs_tx0_symbol" };
+PNAME(mout_phyclk_ufs_rx0_p) = { "fin_pll", "phyclk_ufs_rx0_symbol" };
+PNAME(mout_phyclk_lli_tx0_p) = { "fin_pll", "phyclk_lli_tx0_symbol" };
+PNAME(mout_phyclk_lli_rx0_p) = { "fin_pll", "phyclk_lli_rx0_symbol" };
+PNAME(mout_phyclk_pcie_tx0_p) = { "fin_pll", "phyclk_pcie_tx0" };
+PNAME(mout_phyclk_pcie_rx0_p) = { "fin_pll", "phyclk_pcie_rx0" };
+
+/* fixed rate clocks used in the FSYS0 block */
+struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = {
+	FRATE(0, "phyclk_lli_rx0_symbol", NULL, CLK_IS_ROOT, 150000000),
+	FRATE(0, "phyclk_lli_tx0_symbol", NULL, CLK_IS_ROOT, 150000000),
+	FRATE(0, "phyclk_usbhost20_phy_phyclk_hsic1",
+		NULL, CLK_IS_ROOT, 60000000),
+	FRATE(0, "phyclk_usbhost20_phy_freeclk_hsic1",
+		NULL, CLK_IS_ROOT, 60000000),
+	FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk",
+		NULL, CLK_IS_ROOT, 125000000),
+	FRATE(0, "phyclk_usbdrd300_udrd30_phyclock",
+		NULL, CLK_IS_ROOT, 60000000),
+};
+
+static unsigned long fsys0_clk_regs[] __initdata = {
+	MUX_SEL_FSYS00,
+	MUX_SEL_FSYS01,
+	MUX_SEL_FSYS02,
+	MUX_SEL_FSYS03,
+	DIV_FSYS0,
+	ENABLE_ACLK_FSYS00,
+	ENABLE_ACLK_FSYS01,
+	ENABLE_PCLK_FSYS0,
+	ENABLE_SCLK_FSYS01,
+	ENABLE_SCLK_FSYS02,
+	ENABLE_SCLK_FSYS03,
+	ENABLE_SCLK_FSYS04,
+};
+
+static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
+	MUX(0, "mout_fsys0_phyclk_sel1", mout_fsys0_group_p,
+			MUX_SEL_FSYS00, 16, 2),
+	MUX(0, "mout_fsys0_phyclk_sel0", mout_fsys0_group_p,
+			MUX_SEL_FSYS00, 20, 2),
+	MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
+			MUX_SEL_FSYS00, 24, 1),
+	MUX(0, "mout_hsic_pll_ctrl", mout_hsic_pll_ctrl_p,
+			MUX_SEL_FSYS00, 28, 1),
+
+	MUX(0, "mout_sclk_phy_fsys0_user", mout_sclk_phy_fsys0_p,
+			MUX_SEL_FSYS01, 16, 1),
+	MUX(0, "mout_sclk_ufsunipro11_user", mout_sclk_ufsunipro11_p,
+			MUX_SEL_FSYS01, 20, 1),
+	MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p,
+			MUX_SEL_FSYS01, 24, 1),
+	MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p,
+			MUX_SEL_FSYS01, 28, 1),
+
+	MUX(0, "mout_phyclk_usbhost20_phy_phyclk_hsic1_user",
+			mout_phyclk_usbhost20_phy_phyclk_hsic1_p,
+			MUX_SEL_FSYS02, 16, 1),
+	MUX(0, "mout_phyclk_usbhost20_phy_freeclk_hsic1_user",
+			mout_phyclk_usbhost20_phy_freeclk_hsic1_p,
+			MUX_SEL_FSYS02, 20, 1),
+	MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
+			mout_phyclk_usbdrd300_udrd30_pipe_pclk_p,
+			MUX_SEL_FSYS02, 24, 1),
+	MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
+			mout_phyclk_usbdrd300_udrd30_phyclk_p,
+			MUX_SEL_FSYS02, 28, 1),
+
+	MUX(0, "mout_phyclk_pcie_rx0_user", mout_phyclk_pcie_rx0_p,
+			MUX_SEL_FSYS03, 8, 1),
+	MUX(0, "mout_phyclk_pcie_tx0_user", mout_phyclk_pcie_tx0_p,
+			MUX_SEL_FSYS03, 12, 1),
+	MUX(0, "mout_phyclk_lli_rx0_user", mout_phyclk_lli_rx0_p,
+			MUX_SEL_FSYS03, 16, 1),
+	MUX(0, "mout_phyclk_lli_tx0_user", mout_phyclk_lli_tx0_p,
+			MUX_SEL_FSYS03, 20, 1),
+	MUX(0, "mout_phyclk_ufs_rx0_user", mout_phyclk_ufs_rx0_p,
+			MUX_SEL_FSYS03, 24, 1),
+	MUX(0, "mout_phyclk_ufs_tx0_user", mout_phyclk_ufs_tx0_p,
+			MUX_SEL_FSYS03, 28, 1),
+};
+
+static struct samsung_div_clock fsys0_div_clks[] __initdata = {
+	DIV(0, "dout_pclk_fsys0", "mout_aclk_fsys0_200_user", DIV_FSYS0, 0, 2),
+	DIV(0, "dout_usb20", "mout_hsic_pll", DIV_FSYS0, 4, 4),
+};
+
+static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
+	GATE(ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys0_200_user",
+			ENABLE_ACLK_FSYS01, 28, 0, 0),
+	GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
+			ENABLE_ACLK_FSYS01, 29, 0, 0),
+	GATE(ACLK_UFS11_LINK, "aclk_ufs11_link", "dout_pclk_fsys0",
+			ENABLE_ACLK_FSYS01, 30, 0, 0),
+	GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
+			ENABLE_ACLK_FSYS01, 31, 0, 0),
+
+	GATE(PCLK_GPIO_FSYS0, "pclk_gpio_fsys0", "mout_aclk_fsys0_200_user",
+			ENABLE_PCLK_FSYS0, 24, 0, 0),
+
+	GATE(SCLK_MMC2, "sclk_mmc2_user", "mout_sclk_mmc2_user",
+			ENABLE_SCLK_FSYS01, 24, 0, 0),
+};
+
+static struct samsung_pll_clock fsys0_pll_clks[] __initdata = {
+	PLL(pll_1452x, 0, "fout_hsic_pll", "fin_pll",
+			HSIC_PLL_LOCK, HSIC_PLL_CON0, pll1452x_24mhz_tbl),
+};
+
+static void __init exynos7_clk_fsys0_init(struct device_node *np)
+{
+	struct exynos_cmu_info cmu = {0};
+
+	cmu.pll_clks = fsys0_pll_clks;
+	cmu.nr_pll_clks = ARRAY_SIZE(fsys0_pll_clks);
+	cmu.fixed_clks = fixed_rate_clks_fsys0;
+	cmu.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0);
+	cmu.mux_clks = fsys0_mux_clks;
+	cmu.nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks);
+	cmu.div_clks = fsys0_div_clks;
+	cmu.nr_div_clks = ARRAY_SIZE(fsys0_div_clks);
+	cmu.gate_clks = fsys0_gate_clks;
+	cmu.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks);
+	cmu.nr_clk_ids = FSYS0_NR_CLK;
+	cmu.clk_regs = fsys0_clk_regs;
+	cmu.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs);
+
+	exynos_cmu_register_one(np, &cmu);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
+		exynos7_clk_fsys0_init);
+
+/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
+#define	MUX_SEL_FSYS10			0x0200
+#define	MUX_SEL_FSYS11			0x0204
+#define	MUX_SEL_FSYS12			0x0208
+#define	DIV_FSYS1			0x0600
+#define	ENABLE_ACLK_FSYS1		0x0800
+#define	ENABLE_PCLK_FSYS1		0x0900
+#define	ENABLE_SCLK_FSYS11		0x0A04
+#define	ENABLE_SCLK_FSYS12		0x0A08
+#define	ENABLE_SCLK_FSYS13		0x0A0C
+
+/*
+ * List of parent clocks for Muxes in CMU_FSYS1
+ */
+PNAME(mout_aclk_fsys1_200_p)	= { "fin_pll", "aclk_fsys1_200" };
+PNAME(mout_fsys1_group_p)	= { "fin_pll", "fin_pll_26m",
+				"sclk_phy_fsys1_26m" };
+
+PNAME(mout_sclk_mmc0_p)		= { "fin_pll", "sclk_mmc0" };
+PNAME(mout_sclk_mmc1_p)		= { "fin_pll", "sclk_mmc1" };
+PNAME(mout_sclk_ufsunipro20_p)	= { "fin_pll", "sclk_ufsunipro20" };
+PNAME(mout_sclk_phy_fsys1_p)	= { "fin_pll", "sclk_phy_fsys1" };
+PNAME(mout_sclk_tlx400_wifi1_p)	= { "fin_pll", "sclk_tlx400_wifi1" };
+
+PNAME(mout_phyclk_ufs20_tx0_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" };
+PNAME(mout_phyclk_ufs20_rx0_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
+PNAME(mout_phyclk_ufs20_rx1_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
+
+PNAME(mout_phyclk_pcie_wifi1_tx0_p) = { "fin_pll", "phyclk_pcie_wifi1_tx0" };
+PNAME(mout_phyclk_pcie_wifi1_rx0_p) = { "fin_pll", "phyclk_pcie_wifi1_rx0" };
+
+/* fixed rate clocks used in the FSYS1 block */
+struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = {
+	FRATE(PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
+			NULL, CLK_IS_ROOT, 300000000),
+	FRATE(PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
+			NULL, CLK_IS_ROOT, 300000000),
+	FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol",
+			NULL, CLK_IS_ROOT, 300000000),
+	FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol",
+			NULL, CLK_IS_ROOT, 300000000),
+	FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol",
+			NULL, CLK_IS_ROOT, 300000000),
+};
+
+static unsigned long fsys1_clk_regs[] __initdata = {
+	MUX_SEL_FSYS10,
+	MUX_SEL_FSYS11,
+	MUX_SEL_FSYS12,
+	DIV_FSYS1,
+	ENABLE_ACLK_FSYS1,
+	ENABLE_PCLK_FSYS1,
+	ENABLE_SCLK_FSYS11,
+	ENABLE_SCLK_FSYS12,
+	ENABLE_SCLK_FSYS13,
+};
+
+static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
+	MUX(0, "mout_fsys1_phyclk_sel1", mout_fsys1_group_p,
+			MUX_SEL_FSYS10, 16, 2),
+	MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
+			MUX_SEL_FSYS10, 20, 2),
+	MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
+			MUX_SEL_FSYS10, 28, 1),
+
+	MUX(0, "mout_sclk_tlx400_wifi1_user",
+			mout_sclk_tlx400_wifi1_p, MUX_SEL_FSYS11, 12, 1),
+	MUX(0, "mout_sclk_phy_fsys1_user",
+			mout_sclk_phy_fsys1_p, MUX_SEL_FSYS11, 16, 1),
+	MUX(0, "mout_sclk_ufsunipro20_user",
+			mout_sclk_ufsunipro20_p, MUX_SEL_FSYS11, 20, 1),
+	MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p,
+			MUX_SEL_FSYS11, 24, 1),
+	MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p,
+			MUX_SEL_FSYS11, 28, 1),
+
+	MUX(0, "mout_phyclk_pcie_wifi_rx0_user",
+			mout_phyclk_pcie_wifi1_rx0_p, MUX_SEL_FSYS12, 8, 1),
+	MUX(0, "mout_phyclk_pcie_wifi_tx0_user",
+			mout_phyclk_pcie_wifi1_tx0_p, MUX_SEL_FSYS12, 12, 1),
+	MUX(0, "mout_phyclk_ufs20_rx1_user",
+			mout_phyclk_ufs20_rx1_p, MUX_SEL_FSYS12, 16, 1),
+	MUX(0, "mout_phyclk_ufs20_rx0_user",
+			mout_phyclk_ufs20_rx0_p, MUX_SEL_FSYS12, 24, 1),
+	MUX(0, "mout_phyclk_ufs20_tx0_user",
+			mout_phyclk_ufs20_tx0_p, MUX_SEL_FSYS12, 28, 1),
+};
+
+static struct samsung_div_clock fsys1_div_clks[] __initdata = {
+	DIV(0, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user", DIV_FSYS1, 0, 2),
+};
+
+static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
+	GATE(ACLK_MMC1, "aclk_mmc1", "mout_phyclk_pcie_rx0_user",
+			ENABLE_ACLK_FSYS1, 29, 0, 0),
+	GATE(ACLK_MMC0, "aclk_mmc0", "mout_phyclk_pcie_rx0_user",
+			ENABLE_ACLK_FSYS1, 30, 0, 0),
+	GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_phyclk_pcie_rx0_user",
+			ENABLE_PCLK_FSYS1, 31, 0, 0),
+
+	GATE(SCLK_MMC1, "sclk_mmc1_user", "mout_sclk_mmc1_user",
+			ENABLE_SCLK_FSYS11, 24, 0, 0),
+	GATE(SCLK_MMC0, "sclk_mmc0_user", "mout_sclk_mmc0_user",
+			ENABLE_SCLK_FSYS11, 28, 0, 0),
+};
+
+static void __init exynos7_clk_fsys1_init(struct device_node *np)
+{
+	struct exynos_cmu_info cmu = {0};
+
+	cmu.fixed_clks = fixed_rate_clks_fsys1;
+	cmu.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1);
+	cmu.mux_clks = fsys1_mux_clks;
+	cmu.nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks);
+	cmu.div_clks = fsys1_div_clks;
+	cmu.nr_div_clks = ARRAY_SIZE(fsys1_div_clks);
+	cmu.gate_clks = fsys1_gate_clks;
+	cmu.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks);
+	cmu.nr_clk_ids = FSYS1_NR_CLK;
+	cmu.clk_regs = fsys1_clk_regs;
+	cmu.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs);
+
+	exynos_cmu_register_one(np, &cmu);
+}
+
+CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
+		exynos7_clk_fsys1_init);
+
+/* Register Offset definitions for CMU_DISP (0x13AD0000) */
+#define	DISP_PLL_LOCK			0x0000
+#define	DISP_PLL_CON0			0x0100
+#define	DISP_PLL_CON1			0x0104
+#define	DISP_PLL_CON2			0x0108
+#define	MUX_SEL_DISP0			0x0200
+#define	MUX_SEL_DISP1			0x0204
+#define	MUX_SEL_DISP2			0x0208
+#define	MUX_SEL_DISP3			0x020C
+#define	DIV_DISP			0x0600
+#define	ENABLE_ACLK_DISP			0x0800
+#define	ENABLE_ACLK_DISP_SECURE_SMMU_RO_MMU	0x0804
+#define	ENABLE_ACLK_DISP_SECURE_SMMU_RW_MMU	0x0808
+#define	ENABLE_ACLK_DISP_SECURE_SMMU_RO_SFW	0x080C
+#define	ENABLE_ACLK_DISP_SECURE_SMMU_RW_SFW	0x0810
+#define	ENABLE_PCLK_DISP			0x0900
+#define	ENABLE_PCLK_DISP_SECURE_SMMU_RO_MMU	0x0904
+#define	ENABLE_PCLK_DISP_SECURE_SMMU_RW_MMU	0x0908
+#define	ENABLE_PCLK_DISP_SECURE_SMMU_RO_SFW	0x090C
+#define	ENABLE_PCLK_DISP_SECURE_SMMU_RW_SFW	0x0910
+#define	ENABLE_SCLK_DISP1			0x0A04
+#define	ENABLE_SCLK_DISP2			0x0A08
+
+/*
+ * List of parent clocks for Muxes in CMU_DISP
+ */
+PNAME(mout_aclk_disp_400_p) = { "fin_pll", "aclk_disp_400" };
+PNAME(mout_disp_pll_ctrl_p) = { "fin_pll", "fout_disp_pll" };
+
+PNAME(mout_sclk_dsd_p) = { "fin_pll", "sclk_dsd" };
+
+PNAME(mout_sclk_decon_int_eclk_p) = { "fin_pll", "sclk_decon_int_eclk" };
+PNAME(mout_sclk_decon_ext_eclk_p) = { "fin_pll", "sclk_decon_ext_eclk" };
+PNAME(mout_sclk_decon_vclk_p) = { "fin_pll", "sclk_decon_vclk" };
+
+PNAME(mout_phyclk_hdmiphy_pixel_clko_p)	= { "fin_pll",
+					"phyclk_hdmiphy_clko" };
+PNAME(mout_phyclk_hdmiphy_tmds_clko_p)	= { "fin_pll",
+					"phyclk_hdmiphy_tmds_clko" };
+PNAME(mout_phyclk_mipidphy0_rxclkesc0_p) = { "fin_pll",
+					"phyclk_mipidphy0_rxclkesc0" };
+PNAME(mout_phyclk_mipidphy0_bitclkdiv8_p) = { "fin_pll",
+					"phyclk_mipidphy0_bitclkdiv8" };
+PNAME(mout_phyclk_mipidphy1_rxclkesc0_p) = { "fin_pll",
+					"phyclk_mipidphy1_rxclkesc0" };
+PNAME(mout_phyclk_mipidphy1_bitclkdiv8_p) = { "fin_pll",
+					"phyclk_mipidphy1_bitclkdiv8" };
+
+PNAME(smout_sclk_decon_int_eclk_p) = { "mout_sclk_decon_int_eclk_user",
+					"mout_disp_pll_ctrl" };
+PNAME(smout_sclk_decon_ext_eclk_p) = { "mout_sclk_decon_ext_eclk_user",
+					"mout_disp_pll_ctrl" };
+PNAME(smout_sclk_decon_int_ext_pll_p) = { "mout_sclk_decon_vclk_user",
+					"mout_disp_pll_ctrl" };
+PNAME(smout_sclk_decon_ext_ext_pll_p) = { "mout_sclk_decon_vclk_user",
+					"mout_disp_pll_ctrl" };
+
+/* fixed rate clocks used in the DISP block */
+struct samsung_fixed_rate_clock fixed_rate_clks_disp[] __initdata = {
+	FRATE(0, "phyclk_mipidphy0_rxclkesc0", NULL, CLK_IS_ROOT, 20000000),
+	FRATE(0, "phyclk_mipidphy0_bitclkdiv8", NULL, CLK_IS_ROOT, 187500000),
+	FRATE(0, "phyclk_mipidphy1_rxclkesc0", NULL, CLK_IS_ROOT, 20000000),
+	FRATE(0, "phyclk_mipidphy1_bitclkdiv8", NULL, CLK_IS_ROOT, 187500000),
+	FRATE(0, "sclk_rgb_vclk_dsim0", NULL, CLK_IS_ROOT, 300000000),
+	FRATE(0, "sclk_rgb_vclk_dsim1", NULL, CLK_IS_ROOT, 300000000),
+	FRATE(0, "sclk_decon_ext_vclk", NULL, CLK_IS_ROOT, 300000000),
+	FRATE(0, "phyclk_dpphy_ch3_txd_clk", NULL, CLK_IS_ROOT, 270000000),
+	FRATE(0, "phyclk_dpphy_ch2_txd_clk", NULL, CLK_IS_ROOT, 270000000),
+	FRATE(0, "phyclk_dpphy_ch1_txd_clk", NULL, CLK_IS_ROOT, 270000000),
+	FRATE(0, "phyclk_dpphy_ch0_txd_clk", NULL, CLK_IS_ROOT, 270000000),
+	FRATE(0, "phyclk_hdmi_phy_tmds_clko", NULL, CLK_IS_ROOT, 300000000),
+	FRATE(0, "phyclk_hdmi_phy_pixel_clko", NULL, CLK_IS_ROOT, 300000000),
+};
+
+static unsigned long disp_clk_regs[] __initdata = {
+	MUX_SEL_DISP0,
+	MUX_SEL_DISP1,
+	MUX_SEL_DISP2,
+	MUX_SEL_DISP3,
+	DIV_DISP,
+	ENABLE_ACLK_DISP,
+	ENABLE_ACLK_DISP_SECURE_SMMU_RO_MMU,
+	ENABLE_ACLK_DISP_SECURE_SMMU_RW_MMU,
+	ENABLE_ACLK_DISP_SECURE_SMMU_RO_SFW,
+	ENABLE_ACLK_DISP_SECURE_SMMU_RW_SFW,
+	ENABLE_PCLK_DISP,
+	ENABLE_PCLK_DISP_SECURE_SMMU_RO_MMU,
+	ENABLE_PCLK_DISP_SECURE_SMMU_RW_MMU,
+	ENABLE_PCLK_DISP_SECURE_SMMU_RO_SFW,
+	ENABLE_PCLK_DISP_SECURE_SMMU_RW_SFW,
+	ENABLE_SCLK_DISP1,
+	ENABLE_SCLK_DISP2,
+};
+
+static struct samsung_mux_clock disp_mux_clks[] __initdata = {
+	MUX(0, "mout_disp_pll_ctrl", mout_disp_pll_ctrl_p,
+		MUX_SEL_DISP0, 28, 1),
+	MUX(0, "mout_aclk_disp_400_user", mout_aclk_disp_400_p,
+		MUX_SEL_DISP0, 24, 1),
+
+	MUX(0, "mout_sclk_dsd_user", mout_sclk_dsd_p, MUX_SEL_DISP1, 16, 1),
+	MUX(0, "mout_sclk_decon_vclk_user",
+		mout_sclk_decon_vclk_p, MUX_SEL_DISP1, 20, 1),
+	MUX(0, "mout_sclk_decon_ext_eclk_user",
+		mout_sclk_decon_ext_eclk_p, MUX_SEL_DISP1, 24, 1),
+	MUX(0, "mout_sclk_decon_int_eclk_user",
+		mout_sclk_decon_int_eclk_p, MUX_SEL_DISP1, 28, 1),
+
+	MUX(0, "mout_phyclk_mipidphy1_bitclkdiv8",
+		mout_phyclk_mipidphy1_bitclkdiv8_p, MUX_SEL_DISP2, 0, 1),
+	MUX(0, "mout_phyclk_mipidphy1_rxclkesc0",
+		mout_phyclk_mipidphy1_rxclkesc0_p, MUX_SEL_DISP2, 4, 1),
+	MUX(0, "mout_phyclk_mipidphy0_bitclkdiv8",
+		mout_phyclk_mipidphy0_bitclkdiv8_p, MUX_SEL_DISP2, 8, 1),
+	MUX(0, "mout_phyclk_mipidphy0_rxclkesc0",
+		mout_phyclk_mipidphy0_rxclkesc0_p, MUX_SEL_DISP2, 12, 1),
+	MUX(0, "mout_phyclk_hdmiphy_tmds_clko",
+		mout_phyclk_hdmiphy_tmds_clko_p, MUX_SEL_DISP2, 16, 1),
+	MUX(0, "mout_phyclk_hdmiphy_pixel_clko",
+		mout_phyclk_hdmiphy_pixel_clko_p, MUX_SEL_DISP2, 20, 1),
+
+	MUX(0, "smout_sclk_decon_ext_ext_pll",
+		smout_sclk_decon_ext_ext_pll_p,	MUX_SEL_DISP3, 8, 1),
+	MUX(0, "smout_sclk_decon_int_ext_pll",
+		smout_sclk_decon_int_ext_pll_p, MUX_SEL_DISP3, 12, 1),
+	MUX(0, "smout_sclk_decon_ext_eclk",
+		smout_sclk_decon_ext_eclk_p, MUX_SEL_DISP3, 16, 1),
+	MUX(0, "smout_sclk_decon_int_eclk",
+		smout_sclk_decon_int_eclk_p, MUX_SEL_DISP3, 20, 1),
+};
+
+static struct samsung_div_clock disp_div_clks[] __initdata = {
+	DIV(0, "dout_pclk_disp", "mout_aclk_disp_400_user", DIV_DISP, 0, 2),
+	DIV(0, "sdout_sclk_decon_ext_extclkpll",
+		"smout_sclk_decon_ext_ext_pll",	DIV_DISP, 8, 3),
+	DIV(0, "sdout_sclk_decon_int_extclkpll",
+		"smout_sclk_decon_int_ext_pll", DIV_DISP, 12, 3),
+	DIV(0, "sdout_sclk_decon_ext_eclk",
+		"smout_sclk_decon_ext_eclk", DIV_DISP, 16, 3),
+	DIV(0, "sdout_sclk_decon_int_eclk",
+		"smout_sclk_decon_int_eclk", DIV_DISP, 20, 3),
+};
+
+static struct samsung_gate_clock disp_gate_clks[] __initdata = {
+	GATE(ACLK_CP_DISP, "aclk_cp_disp", "mout_aclk_disp_400_user",
+			ENABLE_ACLK_DISP, 21, 0, 0),
+	GATE(ACLK_DECON_EXT, "aclk_decon_ext", "mout_aclk_disp_400_user",
+			ENABLE_ACLK_DISP, 30, 0, 0),
+	GATE(ACLK_DECON_INT, "aclk_decon_int", "mout_aclk_disp_400_user",
+			ENABLE_ACLK_DISP, 31, 0, 0),
+
+	GATE(ACLK_SMMU_DISP_RO_MMU, "aclk_smmu_disp_ro_mmu",
+			"mout_aclk_disp_400_user",
+			ENABLE_ACLK_DISP_SECURE_SMMU_RO_MMU, 0, 0, 0),
+	GATE(ACLK_SMMU_DISP_RW_MMU, "aclk_smmu_disp_rw_mmu",
+			"mout_aclk_disp_400_user",
+			ENABLE_ACLK_DISP_SECURE_SMMU_RW_MMU, 0, 0, 0),
+	GATE(ACLK_SMMU_DISP_RO_SFW, "aclk_smmu_disp_ro_sfw",
+			"mout_aclk_disp_400_user",
+			ENABLE_ACLK_DISP_SECURE_SMMU_RO_SFW, 0, 0, 0),
+	GATE(ACLK_SMMU_DISP_RW_SFW, "aclk_smmu_disp_rw_sfw",
+			"mout_aclk_disp_400_user",
+			ENABLE_ACLK_DISP_SECURE_SMMU_RW_SFW, 0, 0, 0),
+
+	GATE(PCLK_CP_DISP, "pclk_cp_disp", "dout_pclk_disp",
+			ENABLE_PCLK_DISP, 18, 0, 0),
+	GATE(PCLK_HDMI_PHY, "pclk_hdmi_phy", "dout_pclk_disp",
+			ENABLE_PCLK_DISP, 26, 0, 0),
+	GATE(PCLK_HDMI, "pclk_hdmi", "dout_pclk_disp",
+			ENABLE_PCLK_DISP, 27, 0, 0),
+	GATE(PCLK_DSIM1, "pclk_dsim1", "dout_pclk_disp",
+			ENABLE_PCLK_DISP, 28, 0, 0),
+	GATE(PCLK_DSIM0, "pclk_dsim0", "dout_pclk_disp",
+			ENABLE_PCLK_DISP, 29, 0, 0),
+	GATE(PCLK_DECON_EXT, "pclk_decon_ext", "dout_pclk_disp",
+			ENABLE_PCLK_DISP, 30, 0, 0),
+	GATE(PCLK_DECON_INT, "pclk_decon_int", "dout_pclk_disp",
+			ENABLE_PCLK_DISP, 31, 0, 0),
+
+	GATE(PCLK_SMMU_DISP_RO_MMU, "pclk_smmu_disp_ro_mmu",
+			"mout_aclk_disp_400_user",
+			ENABLE_PCLK_DISP_SECURE_SMMU_RO_MMU, 0, 0, 0),
+	GATE(PCLK_SMMU_DISP_RW_MMU, "pclk_smmu_disp_rw_mmu",
+			"mout_aclk_disp_400_user",
+			ENABLE_PCLK_DISP_SECURE_SMMU_RW_MMU, 0, 0, 0),
+	GATE(PCLK_SMMU_DISP_RO_SFW, "pclk_smmu_disp_ro_sfw",
+			"mout_aclk_disp_400_user",
+			ENABLE_PCLK_DISP_SECURE_SMMU_RO_SFW, 0, 0, 0),
+	GATE(PCLK_SMMU_DISP_RW_SFW, "pclk_smmu_disp_rw_sfw",
+			"mout_aclk_disp_400_user",
+			ENABLE_PCLK_DISP_SECURE_SMMU_RW_SFW, 0, 0, 0),
+
+	GATE(SCLK_DECON_EXT_EXTCLKPLL, "sclk_decon_ext_extclkpll",
+			"sdout_sclk_decon_ext_extclkpll",
+			ENABLE_SCLK_DISP1, 4, 0, 0),
+	GATE(SCLK_DECON_INT_EXTCLKPLL, "sclk_decon_int_extclkpll",
+			"sdout_sclk_decon_int_extclkpll",
+			ENABLE_SCLK_DISP1, 8, 0, 0),
+	GATE(SCLK_HDMI_SPDIF, "sclk_hdmi_spdif_user", "sclk_hdmi_spdif",
+			ENABLE_SCLK_DISP1, 12, 0, 0),
+	GATE(SCLK_DSD, "sclk_dsd_user", "mout_sclk_dsd_user",
+			ENABLE_SCLK_DISP1, 16, 0, 0),
+	GATE(SCLK_DECON_EXT_ECLK, "sclk_decon_ext_eclk_user",
+			"sdout_sclk_decon_ext_eclk",
+			ENABLE_SCLK_DISP1, 24, 0, 0),
+	GATE(SCLK_DECON_INT_ECLK, "sclk_decon_int_eclk_user",
+			"sdout_sclk_decon_int_eclk",
+			ENABLE_SCLK_DISP1, 28, 0, 0),
+
+	GATE(SCLK_RGB_VCLK1, "sclk_rgb_vclk1_user", "sclk_rgb_vclk1",
+			ENABLE_SCLK_DISP2, 24, 0, 0),
+	GATE(SCLK_RGB_VCLK0, "sclk_rgb_vclk0_user", "sclk_rgb_vclk0",
+			ENABLE_SCLK_DISP2, 28, 0, 0),
+};
+
+static struct samsung_pll_clock disp_pll_clks[] __initdata = {
+	PLL(pll_1460x, 0, "fout_disp_pll", "fin_pll",
+		DISP_PLL_LOCK, DISP_PLL_CON0,
+		pll1460x_24mhz_tbl),
+};
+
+static void __init exynos7_clk_disp_init(struct device_node *np)
+{
+	struct exynos_cmu_info cmu = {0};
+
+	cmu.fixed_clks = fixed_rate_clks_disp;
+	cmu.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_disp);
+	cmu.pll_clks = disp_pll_clks;
+	cmu.nr_pll_clks = ARRAY_SIZE(disp_pll_clks);
+	cmu.mux_clks = disp_mux_clks;
+	cmu.nr_mux_clks = ARRAY_SIZE(disp_mux_clks);
+	cmu.div_clks = disp_div_clks;
+	cmu.nr_div_clks = ARRAY_SIZE(disp_div_clks);
+	cmu.gate_clks = disp_gate_clks;
+	cmu.nr_gate_clks = ARRAY_SIZE(disp_gate_clks);
+	cmu.nr_clk_ids = DISP_NR_CLK;
+	cmu.clk_regs = disp_clk_regs;
+	cmu.nr_clk_regs = ARRAY_SIZE(disp_clk_regs);
+
+	exynos_cmu_register_one(np, &cmu);
+}
+
+CLK_OF_DECLARE(exynos7_clk_disp, "samsung,exynos7-clock-disp",
+		exynos7_clk_disp_init);
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
new file mode 100644
index 0000000..15b504a
--- /dev/null
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for blocks TOPC, TOP0 and TOP1,
+ * CCORE, PERIC0, PERIC1 and PERIS, BUS0, BUS1, FSYS0, FSYS1,
+ * Multi media subsystems such as G3D, AUD, DISP, MSCL and
+ * MFC blocks of the Exynos7 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define ACLK_CCORE_532			1
+#define ACLK_CCORE_133			2
+#define ACLK_BUS0_532			3
+#define ACLK_BUS1_532			4
+#define ACLK_BUS1_200			5
+#define ACLK_IMEM_266			6
+#define ACLK_IMEM_200			7
+#define ACLK_IMEM_100			8
+#define ACLK_G2D_400			9
+#define ACLK_G2D_266			10
+#define ACLK_MFC_532			11
+#define ACLK_HEVC_532			12
+#define ACLK_MFC_BUS_532		13
+#define ACLK_MSCL_532			14
+#define ACLK_PERIS_66			15
+#define ACLK_MIF			16
+#define SCLK_CMU_APBIF			17
+#define SCLK_CC_PLL_A			18
+#define SCLK_CC_PLL_B			19
+#define SCLK_BUS0_PLL_A			20
+#define SCLK_BUS0_PLL_B			21
+#define SCLK_BUS0_PLL_MIF		22
+#define SCLK_BUS0_PLL_ATLAS		23
+#define SCLK_BUS_PLL_G3D		24
+#define SCLK_BUS1_PLL_A			25
+#define SCLK_BUS1_PLL_B			26
+#define SCLK_MFC_PLL_A			27
+#define SCLK_MFC_PLL_B			28
+#define SCLK_AUD_PLL			29
+#define CCORE_133_532			30
+#define BUS0_532			31
+#define BUS1_200_532			32
+#define IMEM_100_200_266		33
+#define PERIS_66			34
+#define G2D_266_400		        35
+#define MFC_BUS_532			36
+#define HEVC_532			37
+#define MSCL_532			38
+#define TOPC_NR_CLK			39
+
+/* TOP0 */
+#define CLK_ACLK_MIF			1
+#define CLK_ACLK_VPP1_400		2
+#define CLK_ACLK_VPP0_400		3
+#define CLK_ACLK_PERIC1_66		4
+#define CLK_ACLK_PERIC0_66		5
+#define CLK_ACLK_DISP_400		6
+#define CLK_SCLK_HDMI_SPDIF		7
+#define CLK_SCLK_DSD			8
+#define CLK_SCLK_DECON_VCLK		9
+#define CLK_SCLK_DECON_EXT_ECLK		10
+#define CLK_SCLK_DECON_INT_ECLK		11
+#define CLK_SCLK_SPDIF		        12
+#define CLK_SCLK_PCM1			13
+#define CLK_SCLK_I2S1			14
+#define CLK_SCLK_SPI0			15
+#define CLK_SCLK_SPI1			16
+#define CLK_SCLK_SPI2			17
+#define CLK_SCLK_SPI3			18
+#define CLK_SCLK_SPI4			19
+#define CLK_SCLK_UART0			20
+#define CLK_SCLK_UART1			21
+#define CLK_SCLK_UART2			22
+#define CLK_SCLK_UART3			23
+#define TOP_PERIC			24
+#define TOP_DISP			25
+#define TOP0_NR_CLK			26
+
+/* TOP1 */
+#define CLK_ACLK_MIF3			1
+#define CLK_ACLK_MIF2			2
+#define ACLK_FSYS0_200			3
+#define ACLK_FSYS1_200			4
+#define CLK_SCLK_PHY_FSYS0_26M		5
+#define CLK_SCLK_PHY_FSYS0		6
+#define CLK_SCLK_UFSUNIPRO11		7
+#define CLK_SCLK_MMC2			8
+#define CLK_SCLK_USBDRD300		9
+#define CLK_SCLK_PHY_FSYS1		10
+#define CLK_SCLK_TLX400_WIFI1		11
+#define CLK_SCLK_UFSUNIPRO20		12
+#define CLK_SCLK_MMC1			13
+#define CLK_SCLK_MMC0			14
+#define CLK_SCLK_PHY_FSYS1_26M		15
+#define CLK_FSYS1			16
+#define CLK_FSYS0			17
+#define TOP1_NR_CLK			19
+
+/* CCORE */
+#define ACLK_CC				1
+#define PCLK_RTC			2
+#define CCORE_NR_CLK			3
+
+/* PERIC0 */
+#define PCLK_HSI2C0			1
+#define PCLK_HSI2C1			2
+#define PCLK_HSI2C4			3
+#define PCLK_HSI2C5			4
+#define PCLK_HSI2C9			5
+#define PCLK_HSI2C10			6
+#define PCLK_HSI2C11			7
+#define PCLK_UART0			8
+#define PCLK_ADCIF			9
+#define PCLK_PWM			10
+#define SCLK_PWM			11
+#define SCLK_UART0			12
+#define PERIC0_NR_CLK			13
+
+/* PERIC1 */
+#define PCLK_HSI2C2			1
+#define PCLK_HSI2C3			2
+#define PCLK_HSI2C6			3
+#define PCLK_HSI2C7			4
+#define PCLK_HSI2C8			5
+#define PCLK_UART1			6
+#define PCLK_UART2			7
+#define PCLK_UART3			8
+#define PCLK_SPI0			9
+#define PCLK_SPI1			10
+#define PCLK_SPI2			11
+#define PCLK_SPI3			12
+#define PCLK_SPI4			13
+#define PCLK_I2S1			14
+#define PCLK_PCM1			15
+#define PCLK_SPDIF			16
+#define SCLK_UART1			17
+#define SCLK_UART2			18
+#define SCLK_UART3			19
+#define SCLK_SPI0			20
+#define SCLK_SPI1			21
+#define SCLK_SPI2			22
+#define SCLK_SPI3			23
+#define SCLK_SPI4			24
+#define SCLK_I2S1			25
+#define SCLK_PCM1			27
+#define SCLK_SPDIF			28
+#define IOCLK_I2S1_BCLK			29
+#define IOCLK_SPI0_CLK			30
+#define IOCLK_SPI1_CLK			31
+#define IOCLK_SPI2_CLK			32
+#define IOCLK_SPI3_CLK			33
+#define IOCLK_SPI4_CLK			34
+#define PERIC1_NR_CLK			35
+
+/* PERIS */
+#define PCLK_MCT			1
+#define PCLK_WDT_ATLAS			2
+#define PCLK_SYSREG			3
+#define PCLK_TMU			4
+#define PCLK_CHIPID		        5
+#define SCLK_TMU			6
+#define SCLK_CHIPID			7
+#define PERIS_NR_CLK			8
+
+/* BUS0 */
+#define PCLK_GPIO_BUS0			1
+#define ACLK_LH_DISP0			2
+#define ACLK_LH_DISP1			3
+#define BUS0_NR_CLK			4
+
+/* BUS1 */
+#define PCLK_GPIO_BUS1			1
+#define BUS1_NR_CLK			2
+
+/* FSYS0 */
+#define CLK_PDMA1		1
+#define CLK_PDMA0		2
+#define ACLK_USBHOST20		3
+#define ACLK_USBDRD300		4
+#define ACLK_UFS11_LINK		5
+#define ACLK_MMC2		6
+#define PCLK_GPIO_FSYS0		7
+#define SCLK_MMC2		8
+#define FSYS0_NR_CLK		9
+
+/* FSYS1 */
+#define ACLK_MMC1			1
+#define ACLK_MMC0			2
+#define PCLK_GPIO_FSYS1			3
+#define SCLK_MMC1			4
+#define SCLK_MMC0			5
+#define PHYCLK_UFS_TX0_SYMBOL		6
+#define PHYCLK_UFS_RX0_SYMBOL		7
+#define PHYCLK_UFS20_TX0_SYMBOL		8
+#define PHYCLK_UFS20_RX0_SYMBOL		9
+#define PHYCLK_UFS20_RX1_SYMBOL		10
+#define FSYS1_NR_CLK			11
+
+/* DISP */
+#define ACLK_CP_DISP			1
+#define ACLK_DECON_EXT			2
+#define ACLK_DECON_INT			3
+#define ACLK_SMMU_DISP_RO_MMU		4
+#define ACLK_SMMU_DISP_RW_MMU		5
+#define ACLK_SMMU_DISP_RO_SFW		6
+#define ACLK_SMMU_DISP_RW_SFW		7
+#define PCLK_SMMU_DISP_RO_MMU		8
+#define PCLK_SMMU_DISP_RW_MMU		9
+#define PCLK_SMMU_DISP_RO_SFW		10
+#define PCLK_SMMU_DISP_RW_SFW		11
+#define PCLK_CP_DISP			12
+#define PCLK_HDMI_PHY			13
+#define PCLK_HDMI			14
+#define PCLK_DSIM1			15
+#define PCLK_DSIM0			16
+#define PCLK_DECON_EXT			17
+#define PCLK_DECON_INT			18
+#define SCLK_DECON_EXT_EXTCLKPLL	19
+#define SCLK_DECON_INT_EXTCLKPLL	20
+#define SCLK_HDMI_SPDIF			21
+#define SCLK_DSD			22
+#define SCLK_DECON_EXT_ECLK		23
+#define SCLK_DECON_INT_ECLK		24
+#define SCLK_RGB_VCLK1			25
+#define SCLK_RGB_VCLK0			26
+#define DISP_NR_CLK			27
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
