From patchwork Thu Aug 28 08:01:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Gautam X-Patchwork-Id: 4797111 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 868D9C0338 for ; Thu, 28 Aug 2014 08:05:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 45A392016C for ; Thu, 28 Aug 2014 08:05:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C1365201B9 for ; Thu, 28 Aug 2014 08:05:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965234AbaH1IEm (ORCPT ); Thu, 28 Aug 2014 04:04:42 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:64706 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935486AbaH1ICe (ORCPT ); Thu, 28 Aug 2014 04:02:34 -0400 Received: by mail-pa0-f41.google.com with SMTP id lj1so1526200pab.14 for ; Thu, 28 Aug 2014 01:02:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=A+diS2A1RTilkuFlDZH2+jNERtH6fsryghPZ5k2t1EE=; b=qBH7qYjoZqMihMax1FDXrCBvGuztxTk3Jw6qIr937yEDtiLIti9zfl+Gat0BkeR/O6 UGJN4kLABCXu8LB3eod65UeYxy1iUYKPvZ7N7pHxJBpuwVHnSxOQnggLc/iDexoe812G dufgmqMn1Jp6cLNYhmoDTXTF2oUNMMmZ9uS6YWonqbEGWv11krWf3U2zkwKA0bcs2h8u HE0ufiG4Rgb+b2+VOIUU+dCYxX6tGeD+Q0Uogp7rlp0MzimVGintbG3+z6O9lPga4hMe 6qxVVHcx1dZ1iNmvENxurIRC/Rlu2/YSm/pgkGk9yAOGr+fRg22YlKBye59m3hrlBHBS YojQ== X-Received: by 10.68.220.164 with SMTP id px4mr3260465pbc.102.1409212951746; Thu, 28 Aug 2014 01:02:31 -0700 (PDT) Received: from vivek-linuxpc.sisodomain.com ([14.140.216.146]) by mx.google.com with ESMTPSA id ty8sm10076836pab.26.2014.08.28.01.02.27 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 28 Aug 2014 01:02:30 -0700 (PDT) From: Vivek Gautam To: linux-usb@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, gregkh@linuxfoundation.org, balbi@ti.com, kishon@ti.com, kgene.kim@samsung.com, Vivek Gautam Subject: [PATCH 2/5] phy: exynos5-usbdrd: Add pipe-clk and utmi-clk support Date: Thu, 28 Aug 2014 13:31:57 +0530 Message-Id: <1409212920-28526-3-git-send-email-gautam.vivek@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1409212920-28526-1-git-send-email-gautam.vivek@samsung.com> References: <1409212920-28526-1-git-send-email-gautam.vivek@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exynos7 SoC has now separate gate control for 125MHz pipe3 phy clock, as well as 60MHz utmi phy clock. So get the same and control in the phy-exynos5-usbdrd driver. Signed-off-by: Vivek Gautam --- .../devicetree/bindings/phy/samsung-phy.txt | 4 ++++ drivers/phy/phy-exynos5-usbdrd.c | 24 ++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index 7a6feea..b64d616 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -135,6 +135,10 @@ Required properties: PHY operations, associated by phy name. It is used to determine bit values for clock settings register. For Exynos5420 this is given as 'sclk_usbphy30' in CMU. + - optional clocks: Next gen Exynos SoCs have following additional + gate clocks available: + - phy_pipe: for PIPE3 phy + - phy_utmi: for UTMI+ phy - samsung,pmu-syscon: phandle for PMU system controller interface, used to control pmu registers for power isolation. - #phy-cells : from the generic PHY bindings, must be 1; diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c index b05302b..685c108 100644 --- a/drivers/phy/phy-exynos5-usbdrd.c +++ b/drivers/phy/phy-exynos5-usbdrd.c @@ -148,6 +148,8 @@ struct exynos5_usbdrd_phy_drvdata { * @dev: pointer to device instance of this platform device * @reg_phy: usb phy controller register memory base * @clk: phy clock for register access + * @pipeclk: clock for pipe3 phy + * @utmiclk: clock for utmi+ phy * @drv_data: pointer to SoC level driver data structure * @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY * instances each with its 'phy' and 'phy_cfg'. @@ -161,6 +163,8 @@ struct exynos5_usbdrd_phy { struct device *dev; void __iomem *reg_phy; struct clk *clk; + struct clk *pipeclk; + struct clk *utmiclk; const struct exynos5_usbdrd_phy_drvdata *drv_data; struct phy_usb_instance { struct phy *phy; @@ -446,6 +450,10 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy) dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); + if (!IS_ERR(phy_drd->utmiclk)) + clk_prepare_enable(phy_drd->utmiclk); + if (!IS_ERR(phy_drd->pipeclk)) + clk_prepare_enable(phy_drd->pipeclk); clk_prepare_enable(phy_drd->ref_clk); /* Enable VBUS supply */ @@ -464,6 +472,10 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy) fail_vbus: clk_disable_unprepare(phy_drd->ref_clk); + if (!IS_ERR(phy_drd->pipeclk)) + clk_disable_unprepare(phy_drd->pipeclk); + if (!IS_ERR(phy_drd->utmiclk)) + clk_disable_unprepare(phy_drd->utmiclk); return ret; } @@ -483,6 +495,10 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy) regulator_disable(phy_drd->vbus); clk_disable_unprepare(phy_drd->ref_clk); + if (!IS_ERR(phy_drd->pipeclk)) + clk_disable_unprepare(phy_drd->pipeclk); + if (!IS_ERR(phy_drd->utmiclk)) + clk_disable_unprepare(phy_drd->utmiclk); return 0; } @@ -581,6 +597,14 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) return PTR_ERR(phy_drd->clk); } + phy_drd->pipeclk = devm_clk_get(dev, "phy_pipe"); + if (IS_ERR(phy_drd->pipeclk)) + dev_warn(dev, "Failed to get pipe3 phy operational clock\n"); + + phy_drd->utmiclk = devm_clk_get(dev, "phy_utmi"); + if (IS_ERR(phy_drd->utmiclk)) + dev_warn(dev, "Failed to get utmi phy operational clock\n"); + phy_drd->ref_clk = devm_clk_get(dev, "ref"); if (IS_ERR(phy_drd->ref_clk)) { dev_err(dev, "Failed to get reference clock of usbdrd phy\n");