From patchwork Wed Sep 17 11:50:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Javier Martinez Canillas X-Patchwork-Id: 4923821 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8135D9F3EC for ; Wed, 17 Sep 2014 11:49:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ED69720166 for ; Wed, 17 Sep 2014 11:51:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A4204200DB for ; Wed, 17 Sep 2014 11:51:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755232AbaIQLvU (ORCPT ); Wed, 17 Sep 2014 07:51:20 -0400 Received: from bhuna.collabora.co.uk ([93.93.135.160]:40145 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754363AbaIQLur (ORCPT ); Wed, 17 Sep 2014 07:50:47 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: javier) with ESMTPSA id C84A41708123 From: Javier Martinez Canillas To: Kukjin Kim Cc: Doug Anderson , Chanwoo Choi , Daniel Drake , linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Javier Martinez Canillas Subject: [PATCH 1/2] ARM: dts: Add rtc_src clk for s3c-rtc on exynos Peach boards Date: Wed, 17 Sep 2014 13:50:32 +0200 Message-Id: <1410954633-27025-2-git-send-email-javier.martinez@collabora.co.uk> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1410954633-27025-1-git-send-email-javier.martinez@collabora.co.uk> References: <1410954633-27025-1-git-send-email-javier.martinez@collabora.co.uk> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP commit 546b117fdf17 ("rtc: s3c: add support for RTC of Exynos3250 SoC") added an "rtc_src" DT property for the Samsung's S3C Real Time Clock controller that specifies the 32.768 kHz clock that uses the RTC as its source clock. In the case of the Peach Pit and Pi machines, the Maxim 77802 32kHz AP clock is used as the source clock. Signed-off-by: Javier Martinez Canillas Reviewed-by: Doug Anderson Reviewed-by: Chanwoo Choi --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 5 ++++- arch/arm/boot/dts/exynos5800-peach-pi.dts | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 9a23382..bfd189e 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -12,6 +12,7 @@ #include #include #include +#include #include "exynos5420.dtsi" / { @@ -151,7 +152,7 @@ status = "okay"; clock-frequency = <400000>; - max77802-pmic@9 { + max77802: max77802-pmic@9 { compatible = "maxim,max77802"; interrupt-parent = <&gpx3>; interrupts = <1 IRQ_TYPE_NONE>; @@ -727,6 +728,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; + clock-names = "rtc", "rtc_src"; }; &spi_2 { diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 1d31c81..84ec1ce 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -12,6 +12,7 @@ #include #include #include +#include #include "exynos5800.dtsi" / { @@ -150,7 +151,7 @@ status = "okay"; clock-frequency = <400000>; - max77802-pmic@9 { + max77802: max77802-pmic@9 { compatible = "maxim,max77802"; interrupt-parent = <&gpx3>; interrupts = <1 IRQ_TYPE_NONE>; @@ -715,6 +716,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; + clock-names = "rtc", "rtc_src"; }; &spi_2 {