From patchwork Thu Sep 25 07:05:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 4973381 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4816A9F2BB for ; Thu, 25 Sep 2014 07:05:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 97D072027D for ; Thu, 25 Sep 2014 07:05:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C571E20295 for ; Thu, 25 Sep 2014 07:05:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751412AbaIYHFU (ORCPT ); Thu, 25 Sep 2014 03:05:20 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:50367 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750877AbaIYHFS (ORCPT ); Thu, 25 Sep 2014 03:05:18 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NCG00LN63OQFYC0@mailout2.samsung.com>; Thu, 25 Sep 2014 16:05:14 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.113]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 26.D0.18167.AAEB3245; Thu, 25 Sep 2014 16:05:14 +0900 (KST) X-AuditID: cbfee690-f79ab6d0000046f7-df-5423beaa70fb Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 78.A4.20081.9AEB3245; Thu, 25 Sep 2014 16:05:14 +0900 (KST) Received: from chan.10.32.193.11 ([10.252.81.195]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NCG002LN3OPIB10@mmp2.samsung.com>; Thu, 25 Sep 2014 16:05:13 +0900 (KST) From: Chanwoo Choi To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, mturquette@linaro.org, kgene.kim@samsung.com, tomasz.figa@gmail.com, viresh.kumar@linaro.org, thomas.ab@samsung.com, kyungmin.park@samsung.com, Chanwoo Choi Subject: [PATCHv3 1/4] clk: samsung: exynos3250: Add cpu clock configuration data and instaniate cpu clock Date: Thu, 25 Sep 2014 16:05:04 +0900 Message-id: <1411628707-8496-2-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1411628707-8496-1-git-send-email-cw00.choi@samsung.com> References: <1411628707-8496-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrKLMWRmVeSWpSXmKPExsWyRsSkUHfVPuUQg0WLuCyuf3nOatG74Cqb xdmmN+wWmx5fY7X43HuE0WLG+X1MFk8nXGSz6FjGaLFq1x9Gi41fPRy4PHbOusvucefaHjaP zUvqPfq2rGL0+LxJLoA1issmJTUnsyy1SN8ugSvjw7wXzAVd4hWt75+yNDCuEO5i5OSQEDCR mD77KTOELSZx4d56NhBbSGApo0T7qjyYmvmb3jBBxKczStz5VNjFyAVkNzFJHD+0hBUkwSag JbH/xQ2wZhEBJ4lvR66BNTALPGSUmHjXGcQWFsiReHTsCmMXIwcHi4CqxJ1d/CBhXgEXieN/ 1kDdICfxYc8jdhCbU8BVYuq5J4wQe10kfl9qZAXZKyGwjl1i2+QjYAkWAQGJb5MPsYDMlBCQ ldh0AGqOpMTBFTdYJjAKL2BkWMUomlqQXFCclF5kolecmFtcmpeul5yfu4kRGPqn/z2bsIPx 3gHrQ4wCHIxKPLwe/sohQqyJZcWVuYcYTYE2TGSWEk3OB0ZYXkm8obGZkYWpiamxkbmlmZI4 72upn8FCAumJJanZqakFqUXxRaU5qcWHGJk4OKUaGIVjes1PaGx8t/zq6gp1NRfFlF82UbKH WS7WbnfVFdyQ+7w6vmdeueicS9t7lHIuTum8piC0t+f4IdPGtusNQbJSeskf9q3Qn1K+TcDw qWlTpu7z8BeVAfflhH+1v/z/fe7qVh2DtZ6rbafGuKTdiF3y2Ov31BLzxX92VO1/fHHpy9XP zJ+d8VRiKc5INNRiLipOBAAZ6gz/eAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrAIsWRmVeSWpSXmKPExsVy+t9jQd1V+5RDDI6cYrG4/uU5q0Xvgqts Fmeb3rBbbHp8jdXic+8RRosZ5/cxWTydcJHNomMZo8WqXX8YLTZ+9XDg8tg56y67x51re9g8 Ni+p9+jbsorR4/MmuQDWqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE 3FRbJRefAF23zBygm5QUyhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGR/m vWAu6BKvaH3/lKWBcYVwFyMnh4SAicT8TW+YIGwxiQv31rOB2EIC0xkl7nwq7GLkArKbmCSO H1rCCpJgE9CS2P/iBliRiICTxLcj18CamQUeMkpMvOsMYgsL5Eg8OnaFsYuRg4NFQFXizi5+ kDCvgIvE8T9rmCF2yUl82POIHcTmFHCVmHruCSPEXheJ35caWScw8i5gZFjFKJpakFxQnJSe a6hXnJhbXJqXrpecn7uJERxbz6R2MK5ssDjEKMDBqMTD6+GvHCLEmlhWXJl7iFGCg1lJhHfb VqAQb0piZVVqUX58UWlOavEhRlOgoyYyS4km5wPjPq8k3tDYxMzI0sjc0MLI2FxJnPdAq3Wg kEB6YklqdmpqQWoRTB8TB6dUA+O5zocM3z3jjQ3y+6W+uJruXvnfvV1Klqnt8zRec8vdcwzP +rm3Wh9flFG24cYinWcnnRsmviu+wX5Od49OqJLfBI+1PwPOVGzaW2Yuv5c3MIgn+vGziYd+ pS5hT5v/7BnXo0mZc5PzL/PPmTfV+tXiG8t6Qw6u+FT/5uvaOvMbXdNTbHtXhp5SYinOSDTU Yi4qTgQAmDkTfMMCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add CPU clock configuration data and instantiate the CPU clock type for Exynos3250 to support Samsung specific cpu-clock type. Signed-off-by: Chanwoo Choi Acked-by: Kyungmin Park Cc: Tomasz Figa Cc: Thomas Abraham Cc: Kukjin Kim --- drivers/clk/samsung/clk-cpu.h | 4 ++++ drivers/clk/samsung/clk-exynos3250.c | 19 +++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index 42e1905..1ba31eb 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -13,6 +13,10 @@ #include "clk.h" +#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \ + (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ + ((corem) << 4)) + #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \ (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ ((periph) << 12) | ((corem1) << 8) | ((corem0) << 4)) diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index 6e6cca3..aa55218 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -19,6 +19,7 @@ #include #include "clk.h" +#include "clk-cpu.h" #include "clk-pll.h" #define SRC_LEFTBUS 0x4200 @@ -793,6 +794,20 @@ static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = { UPLL_LOCK, UPLL_CON0, NULL), }; +static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = { + { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E4210_CPU_DIV1(7, 7), }, + { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E4210_CPU_DIV1(7, 7), }, + { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E4210_CPU_DIV1(7, 7), }, + { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E4210_CPU_DIV1(7, 7), }, + { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E4210_CPU_DIV1(7, 7), }, + { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E4210_CPU_DIV1(7, 7), }, + { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E4210_CPU_DIV1(7, 7), }, + { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E4210_CPU_DIV1(7, 7), }, + { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E4210_CPU_DIV1(7, 7), }, + { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E4210_CPU_DIV1(7, 7), }, + { 0 }, +}; + static void __init exynos3_core_down_clock(void) { unsigned int tmp; @@ -840,6 +855,10 @@ static void __init exynos3250_cmu_init(struct device_node *np) samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks)); samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks)); samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks)); + exynos_register_cpu_clock(ctx, CLK_DIV_CORE2, "armclk", + mout_core_p[0], mout_core_p[1], 0x14200, + e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d), + CLK_CPU_HAS_DIV1); exynos3_core_down_clock();