From patchwork Mon Sep 29 05:15:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 4993451 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2B8E59F2BA for ; Mon, 29 Sep 2014 05:15:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 43BE920266 for ; Mon, 29 Sep 2014 05:15:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 29CA820265 for ; Mon, 29 Sep 2014 05:15:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751594AbaI2FPt (ORCPT ); Mon, 29 Sep 2014 01:15:49 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:25262 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751556AbaI2FPr (ORCPT ); Mon, 29 Sep 2014 01:15:47 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NCN00LZYDAA9N20@mailout2.samsung.com>; Mon, 29 Sep 2014 14:15:46 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.122]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 7D.47.19034.10BE8245; Mon, 29 Sep 2014 14:15:45 +0900 (KST) X-AuditID: cbfee691-f79b86d000004a5a-48-5428eb016594 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 28.5A.09430.10BE8245; Mon, 29 Sep 2014 14:15:45 +0900 (KST) Received: from abhilash-ubuntu.sisodomain.com ([107.108.73.92]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NCN00D5ED9MLG20@mmp2.samsung.com>; Mon, 29 Sep 2014 14:15:45 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, catalin.marinas@arm.com, robh@kernel.org, devicetree@vger.kernel.org, tomasz.figa@gmail.com, linus.walleij@linaro.org Subject: [PATCH v3 1/6] pinctrl: exynos: Generalize the eint16_31 demux code Date: Mon, 29 Sep 2014 10:45:07 +0530 Message-id: <1411967712-8321-2-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1411967712-8321-1-git-send-email-a.kesavan@samsung.com> References: <1411967712-8321-1-git-send-email-a.kesavan@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrDLMWRmVeSWpSXmKPExsWyRsSkSpfxtUaIwfodUhbvl/UwWsw/co7V Ysqf5UwWmx5fY7WYcX4fk8X/PTvYLVbt+sPowO6xZt4aRo+ds+6ye2xa1cnmcefaHjaPzUvq PT5vkgtgi+KySUnNySxLLdK3S+DKONd0jbFgplzFlo5ZzA2MGyS7GDk5JARMJO5O28ACYYtJ XLi3nq2LkYtDSGApo8SCjcdYYYoe3t0JViQkMJ1R4skGI4iiPiaJL883MoMk2AT0JBb8+wpm iwhoSEzpeswOYjMLLGCU6Gup6WLk4BAW8JG43Z0LEmYRUJX4MX8KG4jNK+AicfzfMjaQEgkB BYk5k2xAwpwCrhKLuzYzgYSFgEpevAM7TUJgEbvEmsOL2CDGCEh8m3yIBaJVVmLTAWaIiyUl Dq64wTKBUXgBI8MqRtHUguSC4qT0IlO94sTc4tK8dL3k/NxNjMBAP/3v2cQdjPcPWB9iFOBg VOLh5VihESLEmlhWXJl7iNEUaMNEZinR5HxgPOWVxBsamxlZmJqYGhuZW5opifPqSP8MFhJI TyxJzU5NLUgtii8qzUktPsTIxMEp1cA4ydRLfqlDvnPanm9KiuHc8mXf9FjUb2+ZdK945ZId uVbrn64UW7fyFjO3+Y6s6O/3zwTeb4zcahOoNXnjpugNMznaOX2END62/l5SMD2p7yyfrJJ9 3et9x5ZkC/5mrb97LXtX7c+ewtigl/4309cv8Bf+O/nmHNZTt/5smNjJeepIp2TFwr3eSizF GYmGWsxFxYkAaj7TE28CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGIsWRmVeSWpSXmKPExsVy+t9jQV3G1xohBu/fC1q8X9bDaDH/yDlW iyl/ljNZbHp8jdVixvl9TBb/9+xgt1i16w+jA7vHmnlrGD12zrrL7rFpVSebx51re9g8Ni+p 9/i8SS6ALaqB0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnFJ0DX LTMH6BYlhbLEnFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGENY8a5pmuMBTPlKrZ0 zGJuYNwg2cXIySEhYCLx8O5OFghbTOLCvfVsILaQwHRGiScbjLoYuYDsPiaJL883MoMk2AT0 JBb8+wpmiwhoSEzpeswOYjMLLGCU6Gup6WLk4BAW8JG43Z0LEmYRUJX4MX8K2ExeAReJ4/+W sYGUSAgoSMyZZAMS5hRwlVjctZkJJCwEVPLiHdsERt4FjAyrGEVTC5ILipPSc430ihNzi0vz 0vWS83M3MYLj6Jn0DsZVDRaHGAU4GJV4eDlWaIQIsSaWFVfmHmKU4GBWEuFVeK0eIsSbklhZ lVqUH19UmpNafIjRFOimicxSosn5wBjPK4k3NDYxNzU2tTSxMDGzVBLnPdhqHSgkkJ5Ykpqd mlqQWgTTx8TBKdXAWK168+kSw81pjnMip6dKF3rkRm3f5sTPLBLwQ/T0mwTugmmfDNefdItu +ilY+2RSg3XDDM61Bs85lu3Z5Ptiy4IbgVsjzH9Y67Lf1KkwFXrFIN666pOh59+FvPnxp5Ln N7c3ywaW5106F34kv+3yx5sfQ/OOhV98a/S7slOvZEJnLFO54zc7JZbijERDLeai4kQA2TJn 6rkCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external interrupt pending status and mask registers. So this function is not extensible for Exynos7 SoC which has these registers at different offsets. Generalize the exynos_irq_demux_eint16_31 function by using the pending/mask register offset values from the exynos_irq_chip structure. This is done by adding a irq_chip field to the samsung_pin_bank struct. Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Cc: Tomasz Figa Cc: Linus Walleij --- drivers/pinctrl/samsung/pinctrl-exynos.c | 14 ++++++++++---- drivers/pinctrl/samsung/pinctrl-samsung.h | 2 ++ 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index d7154ed..14b9b44 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -260,7 +260,7 @@ static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, struct samsung_pin_bank *b = h->host_data; irq_set_chip_data(virq, b); - irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip, + irq_set_chip_and_handler(virq, &b->irq_chip->chip, handle_level_irq); set_irq_flags(virq, IRQF_VALID); return 0; @@ -344,6 +344,8 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) ret = -ENOMEM; goto err_domains; } + + bank->irq_chip = &exynos_gpio_irq_chip; } return 0; @@ -445,9 +447,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) for (i = 0; i < eintd->nr_banks; ++i) { struct samsung_pin_bank *b = eintd->banks[i]; - pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET + pend = readl(d->virt_base + b->irq_chip->eint_pend + b->eint_offset); - mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET + mask = readl(d->virt_base + b->irq_chip->eint_mask + b->eint_offset); exynos_irq_demux_eint(pend & ~mask, b->irq_domain); } @@ -458,7 +460,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { - irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip, + struct samsung_pin_bank *b = h->host_data; + + irq_set_chip_and_handler(virq, &b->irq_chip->chip, handle_level_irq); irq_set_chip_data(virq, h->host_data); set_irq_flags(virq, IRQF_VALID); @@ -510,6 +514,8 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) return -ENXIO; } + bank->irq_chip = &exynos_wkup_irq_chip; + if (!of_find_property(bank->of_node, "interrupts", NULL)) { bank->eint_type = EINT_TYPE_WKUP_MUX; ++muxed_banks; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 5cedc9d..d2c38c8 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -127,6 +127,7 @@ struct samsung_pin_bank_type { * @irq_domain: IRQ domain of the bank. * @gpio_chip: GPIO chip of the bank. * @grange: linux gpio pin range supported by this bank. + * @irq_chip: link to irq chip for external gpio and wakeup interrupts. * @slock: spinlock protecting bank registers * @pm_save: saved register values during suspend */ @@ -146,6 +147,7 @@ struct samsung_pin_bank { struct irq_domain *irq_domain; struct gpio_chip gpio_chip; struct pinctrl_gpio_range grange; + struct exynos_irq_chip *irq_chip; spinlock_t slock; u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/