From patchwork Thu Oct 9 13:54:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 5058321 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E14659F40F for ; Thu, 9 Oct 2014 13:56:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 04016201ED for ; Thu, 9 Oct 2014 13:56:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 00888201C8 for ; Thu, 9 Oct 2014 13:56:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752628AbaJIN43 (ORCPT ); Thu, 9 Oct 2014 09:56:29 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:56031 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751608AbaJIN42 (ORCPT ); Thu, 9 Oct 2014 09:56:28 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0ND600F1XK22FUD0@mailout1.samsung.com>; Thu, 09 Oct 2014 22:56:26 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.123]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 48.CB.11124.A0496345; Thu, 09 Oct 2014 22:56:26 +0900 (KST) X-AuditID: cbfee68e-f79b46d000002b74-cd-5436940ad606 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 62.9B.20081.A0496345; Thu, 09 Oct 2014 22:56:26 +0900 (KST) Received: from abhilash-ubuntu.sisodomain.com ([107.108.73.92]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0ND6004PBJZ78R60@mmp2.samsung.com>; Thu, 09 Oct 2014 22:56:26 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org, tomasz.figa@gmail.com, linus.walleij@linaro.org Cc: linux-samsung-soc@vger.kernel.org, catalin.marinas@arm.com, naveenkrishna.ch@gmail.com, robh@kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 1/6] pinctrl: exynos: Generalize the eint16_31 demux code Date: Thu, 09 Oct 2014 19:24:29 +0530 Message-id: <1412862874-9335-2-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1412862874-9335-1-git-send-email-a.kesavan@samsung.com> References: <1412862874-9335-1-git-send-email-a.kesavan@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCLMWRmVeSWpSXmKPExsWyRsSkWpdrilmIwapF6hbvl/UwWsw/co7V Ysqf5UwWmx5fY7WYcX4fk8Wibf+ZLf7v2cFusWrXH0YHDo8189YweuycdZfdY9OqTjaPO9f2 sHlsXlLv8XmTXABbFJdNSmpOZllqkb5dAlfGsv8b2Qvmy1Vc3XybqYFxm2QXIyeHhICJxPLW J4wQtpjEhXvr2boYuTiEBJYySqw8MZ8dpqhz7UMmiMR0RokF1y6xQDh9TBJnWzrB2tkE9CQW /PvKDGKLCERLLNvzlx2kiFmgk1Hi7dppTCAJYQEfiaX/n7OA2CwCqhJPb8xkBbF5BVwkNj3/ DGRzAK1TkJgzyQbE5BRwlZjcGQxSIQRU8ev9P7CREgLr2CV2bZ8NNUZA4tvkQywQrbISmw4w QxwtKXFwxQ2WCYzCCxgZVjGKphYkFxQnpRcZ6RUn5haX5qXrJefnbmIEBv7pf8/6djDePGB9 iFGAg1GJh/fBP9MQIdbEsuLK3EOMpkAbJjJLiSbnA+MrryTe0NjMyMLUxNTYyNzSTEmcN0Hq Z7CQQHpiSWp2ampBalF8UWlOavEhRiYOTqkGRuMnGxdfUNZKY2jxDVeqLf23aoepzrerWypD Z4Wuzvz97ed2/93TF3hdN1yat6dEh1F3036LLX8FLni27VAqt+h82bt9xrOgIuM/+tOTXi95 ofDsy/mTstXP2T5fWhx8ZYZpjefhfX7KbOlWahVh5qVmziKrV8rGqBxIYJDkT8rZdNFsecS7 z0osxRmJhlrMRcWJAPPaIMt3AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHIsWRmVeSWpSXmKPExsVy+t9jQV2uKWYhBm0t8hbvl/UwWsw/co7V Ysqf5UwWmx5fY7WYcX4fk8Wibf+ZLf7v2cFusWrXH0YHDo8189YweuycdZfdY9OqTjaPO9f2 sHlsXlLv8XmTXABbVAOjTUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqt kotPgK5bZg7QQUoKZYk5pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqMDNBAwhrGjGX/N7IX zJeruLr5NlMD4zbJLkZODgkBE4nOtQ+ZIGwxiQv31rN1MXJxCAlMZ5RYcO0SC4TTxyRxtqWT EaSKTUBPYsG/r8wgtohAtMSyPX/ZQYqYBToZJd6unQY2SljAR2Lp/+csIDaLgKrE0xszWUFs XgEXiU3PPwPZHEDrFCTmTLIBMTkFXCUmdwaDVAgBVfx6/499AiPvAkaGVYyiqQXJBcVJ6bmG esWJucWleel6yfm5mxjBcfVMagfjygaLQ4wCHIxKPLwP/pmGCLEmlhVX5h5ilOBgVhLhfZNl FiLEm5JYWZValB9fVJqTWnyI0RToponMUqLJ+cCYzyuJNzQ2MTc1NrU0sTAxs1QS5z3Qah0o JJCeWJKanZpakFoE08fEwSnVwHj8ev2061YrC8M3v35tzPIy/9HkZU/2Zt0SX9S0uqA4hmGx 9Yd1Br5eSv9cIyexnP39teDv4+URV1++bnjNqbvyH8uPeZunOUUefzL1zse5Ks2aXZHbiqe1 sp+8P5fhfpLuxNBN6ksXLV4we8P+uKadlcINjmyC3hI3jb6fz922e4nejsURyQ4BSizFGYmG WsxFxYkA5mgRB8ECAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The function exynos_irq_demux_eint16_31 uses pre-defined offsets for external interrupt pending status and mask registers. So this function is not extensible for Exynos7 SoC which has these registers at different offsets. Generalize the exynos_irq_demux_eint16_31 function by using the pending/mask register offset values from the exynos_irq_chip structure. This is done by adding a irq_chip field to the samsung_pin_bank struct. Signed-off-by: Abhilash Kesavan Reviewed-by: Thomas Abraham Tested-by: Thomas Abraham Acked-by: Tomasz Figa Cc: Linus Walleij --- drivers/pinctrl/samsung/pinctrl-exynos.c | 14 ++++++++++---- drivers/pinctrl/samsung/pinctrl-samsung.h | 2 ++ 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 6190106..0cca117 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -260,7 +260,7 @@ static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, struct samsung_pin_bank *b = h->host_data; irq_set_chip_data(virq, b); - irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip, + irq_set_chip_and_handler(virq, &b->irq_chip->chip, handle_level_irq); set_irq_flags(virq, IRQF_VALID); return 0; @@ -343,6 +343,8 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) ret = -ENOMEM; goto err_domains; } + + bank->irq_chip = &exynos_gpio_irq_chip; } return 0; @@ -444,9 +446,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) for (i = 0; i < eintd->nr_banks; ++i) { struct samsung_pin_bank *b = eintd->banks[i]; - pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET + pend = readl(d->virt_base + b->irq_chip->eint_pend + b->eint_offset); - mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET + mask = readl(d->virt_base + b->irq_chip->eint_mask + b->eint_offset); exynos_irq_demux_eint(pend & ~mask, b->irq_domain); } @@ -457,7 +459,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { - irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip, + struct samsung_pin_bank *b = h->host_data; + + irq_set_chip_and_handler(virq, &b->irq_chip->chip, handle_level_irq); irq_set_chip_data(virq, h->host_data); set_irq_flags(virq, IRQF_VALID); @@ -509,6 +513,8 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) return -ENXIO; } + bank->irq_chip = &exynos_wkup_irq_chip; + if (!of_find_property(bank->of_node, "interrupts", NULL)) { bank->eint_type = EINT_TYPE_WKUP_MUX; ++muxed_banks; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index ec43b7d..3076b8b 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -151,6 +151,7 @@ struct samsung_pin_bank_data { * @irq_domain: IRQ domain of the bank. * @gpio_chip: GPIO chip of the bank. * @grange: linux gpio pin range supported by this bank. + * @irq_chip: link to irq chip for external gpio and wakeup interrupts. * @slock: spinlock protecting bank registers * @pm_save: saved register values during suspend */ @@ -171,6 +172,7 @@ struct samsung_pin_bank { struct irq_domain *irq_domain; struct gpio_chip gpio_chip; struct pinctrl_gpio_range grange; + struct exynos_irq_chip *irq_chip; spinlock_t slock; u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/