| Message ID | 1416842312-4405-3-git-send-email-k.kozlowski@samsung.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
Hi Krzysztof, Please see my comments inline. 2014-11-25 0:18 GMT+09:00 Krzysztof Kozlowski <k.kozlowski@samsung.com>: > +static int audss_clk_gate_enable(struct clk_hw *hw) > +{ > + int ret; > + > + if (!IS_ERR(pll_in)) > + clk_prepare_enable(pll_in); Calling clk_prepare_enable() from enable() callback doesn't look like a good idea, because enabling is not supposed to sleep, while preparing might do so. I guess you have to pre-prepare this clock in probe and then only call enable here. > + ret = clk_gate_ops.enable(hw); > + if (!IS_ERR(pll_in)) > + clk_disable_unprepare(pll_in); > + > + return ret; > +} [snip] > +/* TODO: Also mux and div */ > +const struct clk_ops audss_clk_gate_ops = { nit: static const probably? > + .enable = audss_clk_gate_enable, > + .disable = audss_clk_gate_disable, > + .is_enabled = audss_clk_gate_is_enabled, > +}; As for the approach itself, maybe you should simply register fully custom clocks with clk_register(), without altering clk_register_gate() at all and simply calling gate ops whenever necessary? I don't know, just a loose idea. By the way, this issue could be probably solved by integrating generic clocks with regmap API, since regmap-mmio can automatically control a clock. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On wto, 2014-11-25 at 20:35 +0900, Tomasz Figa wrote: > Hi Krzysztof, > > Please see my comments inline. > > 2014-11-25 0:18 GMT+09:00 Krzysztof Kozlowski <k.kozlowski@samsung.com>: > > +static int audss_clk_gate_enable(struct clk_hw *hw) > > +{ > > + int ret; > > + > > + if (!IS_ERR(pll_in)) > > + clk_prepare_enable(pll_in); > > Calling clk_prepare_enable() from enable() callback doesn't look like > a good idea, because enabling is not supposed to sleep, while > preparing might do so. Right. > I guess you have to pre-prepare this clock in probe and then only call > enable here. Yes, the prepare won't have any negative effect on energy usage anyway. > > > + ret = clk_gate_ops.enable(hw); > > + if (!IS_ERR(pll_in)) > > + clk_disable_unprepare(pll_in); > > + > > + return ret; > > +} > > [snip] > > > +/* TODO: Also mux and div */ > > +const struct clk_ops audss_clk_gate_ops = { > > nit: static const probably? Yes. > > > + .enable = audss_clk_gate_enable, > > + .disable = audss_clk_gate_disable, > > + .is_enabled = audss_clk_gate_is_enabled, > > +}; > > As for the approach itself, maybe you should simply register fully > custom clocks with clk_register(), without altering > clk_register_gate() at all and simply calling gate ops whenever > necessary? I don't know, just a loose idea. Initially that seemed to me the simplest way to encapsulate gate_ops calls. However in that approach I should also change clk_register_mux and clk_register_divider... which complicates this patch and maybe your idea will be simpler overall. > By the way, this issue could be probably solved by integrating generic > clocks with regmap API, since regmap-mmio can automatically control a > clock. Indeed but this looks like much bigger task. Anyway thanks for feedback. I'll prepare another version. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index acce708ace18..d10286f30b4f 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -29,6 +29,7 @@ static DEFINE_SPINLOCK(lock); static struct clk **clk_table; static void __iomem *reg_base; static struct clk_onecell_data clk_data; +struct clk *pll_in; #define ASS_CLK_SRC 0x0 #define ASS_CLK_DIV 0x4 @@ -75,6 +76,48 @@ static const struct of_device_id exynos_audss_clk_of_match[] = { {}, }; +static int audss_clk_gate_enable(struct clk_hw *hw) +{ + int ret; + + if (!IS_ERR(pll_in)) + clk_prepare_enable(pll_in); + ret = clk_gate_ops.enable(hw); + if (!IS_ERR(pll_in)) + clk_disable_unprepare(pll_in); + + return ret; +} + +static void audss_clk_gate_disable(struct clk_hw *hw) +{ + if (!IS_ERR(pll_in)) + clk_prepare_enable(pll_in); + clk_gate_ops.disable(hw); + if (!IS_ERR(pll_in)) + clk_disable_unprepare(pll_in); +} + +static int audss_clk_gate_is_enabled(struct clk_hw *hw) +{ + int ret; + + if (!IS_ERR(pll_in)) + clk_prepare_enable(pll_in); + ret = clk_gate_ops.is_enabled(hw); + if (!IS_ERR(pll_in)) + clk_disable_unprepare(pll_in); + + return ret; +} + +/* TODO: Also mux and div */ +const struct clk_ops audss_clk_gate_ops = { + .enable = audss_clk_gate_enable, + .disable = audss_clk_gate_disable, + .is_enabled = audss_clk_gate_is_enabled, +}; + /* register exynos_audss clocks */ static int exynos_audss_clk_probe(struct platform_device *pdev) { @@ -83,7 +126,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; const char *sclk_pcm_p = "sclk_pcm0"; - struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; + struct clk *pll_ref, *cdclk, *sclk_audio, *sclk_pcm_in; const struct of_device_id *match; enum exynos_audss_clk_type variant; @@ -145,33 +188,33 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0, &lock); - clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk", + clk_table[EXYNOS_SRP_CLK] = clk_register_gate_ops(NULL, "srp_clk", "dout_srp", CLK_SET_RATE_PARENT, - reg_base + ASS_CLK_GATE, 0, 0, &lock); + reg_base + ASS_CLK_GATE, 0, 0, &lock, &audss_clk_gate_ops); - clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus", + clk_table[EXYNOS_I2S_BUS] = clk_register_gate_ops(NULL, "i2s_bus", "dout_aud_bus", CLK_SET_RATE_PARENT, - reg_base + ASS_CLK_GATE, 2, 0, &lock); + reg_base + ASS_CLK_GATE, 2, 0, &lock, &audss_clk_gate_ops); - clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s", + clk_table[EXYNOS_SCLK_I2S] = clk_register_gate_ops(NULL, "sclk_i2s", "dout_i2s", CLK_SET_RATE_PARENT, - reg_base + ASS_CLK_GATE, 3, 0, &lock); + reg_base + ASS_CLK_GATE, 3, 0, &lock, &audss_clk_gate_ops); - clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus", + clk_table[EXYNOS_PCM_BUS] = clk_register_gate_ops(NULL, "pcm_bus", "sclk_pcm", CLK_SET_RATE_PARENT, - reg_base + ASS_CLK_GATE, 4, 0, &lock); + reg_base + ASS_CLK_GATE, 4, 0, &lock, &audss_clk_gate_ops); sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); if (!IS_ERR(sclk_pcm_in)) sclk_pcm_p = __clk_get_name(sclk_pcm_in); - clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", + clk_table[EXYNOS_SCLK_PCM] = clk_register_gate_ops(NULL, "sclk_pcm", sclk_pcm_p, CLK_SET_RATE_PARENT, - reg_base + ASS_CLK_GATE, 5, 0, &lock); + reg_base + ASS_CLK_GATE, 5, 0, &lock, &audss_clk_gate_ops); if (variant == TYPE_EXYNOS5420) { - clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma", + clk_table[EXYNOS_ADMA] = clk_register_gate_ops(NULL, "adma", "dout_srp", CLK_SET_RATE_PARENT, - reg_base + ASS_CLK_GATE, 9, 0, &lock); + reg_base + ASS_CLK_GATE, 9, 0, &lock, &audss_clk_gate_ops); } for (i = 0; i < clk_data.clk_num; i++) {
Audio subsystem clocks are located in separate block. If parent clock (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block. This was observed on Exynos 5420 platforms (Arndale Octa and Peach Pi/Pit) after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated (no users). The system hang on disabling unused clocks from audss block. Whenever system wants to operate on audss clock it has to enable epll clock. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reported-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reported-by: Kevin Hilman <khilman@kernel.org> --- drivers/clk/samsung/clk-exynos-audss.c | 69 +++++++++++++++++++++++++++------- 1 file changed, 56 insertions(+), 13 deletions(-)