From patchwork Wed Nov 26 11:17:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 5384781 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B25FFC11AC for ; Wed, 26 Nov 2014 11:19:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 36189201EC for ; Wed, 26 Nov 2014 11:19:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0B85C200EC for ; Wed, 26 Nov 2014 11:18:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752188AbaKZLS5 (ORCPT ); Wed, 26 Nov 2014 06:18:57 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:57496 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751118AbaKZLS4 (ORCPT ); Wed, 26 Nov 2014 06:18:56 -0500 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NFN003UC8RJRI70@mailout2.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 26 Nov 2014 20:18:55 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 7B.15.17016.F17B5745; Wed, 26 Nov 2014 20:18:55 +0900 (KST) X-AuditID: cbfee68d-f79296d000004278-ec-5475b71f6554 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id FA.9C.20081.E17B5745; Wed, 26 Nov 2014 20:18:55 +0900 (KST) Received: from abhilash-ubuntu.sisodomain.com ([107.108.73.92]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NFN00FF48PKTQE0@mmp2.samsung.com>; Wed, 26 Nov 2014 20:18:54 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, mturquette@linaro.org Cc: linux-samsung-soc@vger.kernel.org, kesavan.abhilash@gmail.com Subject: [PATCH 3/4] clk: samsung: add cpu clock support for Exynos7 Date: Wed, 26 Nov 2014 16:47:50 +0530 Message-id: <1417000671-11996-4-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1417000671-11996-1-git-send-email-a.kesavan@samsung.com> References: <1417000671-11996-1-git-send-email-a.kesavan@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMLMWRmVeSWpSXmKPExsWyRsSkSld+e2mIwY8PPBZr/ipZbHp8jdVi xvl9TBZPJ1xkszj8pp3VYtWuP4wObB47Z91l97hzbQ+bx+Yl9R59W1YxenzeJBfAGsVlk5Ka k1mWWqRvl8CVMevdI/aCr5EVtzZOZ2xgvOLVxcjJISFgIrG25ywThC0mceHeerYuRi4OIYGl jBIrp79lhik6eW8XK0RiOqPE+955UFV9TBKzz58Da2cT0JNY8O8rWIeIQIHE6ZkzwGxmAUeJ Vd/nAtVwcAgLuEj82eECEmYRUJVYeHYJI4jNK+Aq0fXkOQtIiYSAgsScSTYgYU4BN4kV29ex gNhCQCX3jj0GWysh0M8u8eXlRnaIOQIS3yYfguqVldh0AOpmSYmDK26wTGAUXsDIsIpRNLUg uaA4Kb3IUK84Mbe4NC9dLzk/dxMjMKxP/3vWu4Px9gHrQ4wCHIxKPLwRUqUhQqyJZcWVuYcY TYE2TGSWEk3OB0ZPXkm8obGZkYWpiamxkbmlmZI4r6LUz2AhgfTEktTs1NSC1KL4otKc1OJD jEwcnFINjHNZny83LDz0J0fpTtS3g4le3J+sBZbbXHbW3Wm+aMLtc2vCerfmnE9/FHGFXSJn z+KFdVv1bvDomegeid8ixN5z6XNMbl8i06qb1VW8NrN8rqVM3Rz4aVqX288TC3rWlv46csr+ pftm3sL2B/4zU7Vym2zTWZ5s18raJrZ47uf5KRxv9/C1MiuxFGckGmoxFxUnAgAggnt1ZgIA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLIsWRmVeSWpSXmKPExsVy+t9jQV357aUhBt23mSzW/FWy2PT4GqvF jPP7mCyeTrjIZnH4TTurxapdfxgd2Dx2zrrL7nHn2h42j81L6j36tqxi9Pi8SS6ANaqB0SYj NTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnFJ0DXLTMH6AAlhbLEnFKg UEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGENY8asd4/YC75GVtzaOJ2xgfGKVxcjJ4eE gInEyXu7WCFsMYkL99azdTFycQgJTGeUeN87D8rpY5KYff4cE0gVm4CexIJ/X5lBbBGBAonT M2eA2cwCjhKrvs8FquHgEBZwkfizwwUkzCKgKrHw7BJGEJtXwFWi68lzFpASCQEFiTmTbEDC nAJuEiu2r2MBsYWASu4de8w2gZF3ASPDKkbR1ILkguKk9FxDveLE3OLSvHS95PzcTYzgqHkm tYNxZYPFIUYBDkYlHt4IqdIQIdbEsuLK3EOMEhzMSiK8XzcAhXhTEiurUovy44tKc1KLDzGa Ah01kVlKNDkfGNF5JfGGxibmpsamliYWJmaWSuK8N27mhggJpCeWpGanphakFsH0MXFwSjUw pvQ1dcewN9yTE+ew6JM6888qp/dfU2rbNF4rm9ObnzdN99Gf72+RyL4yPbo9+O3iMHt+7Qy+ 4vvct94clf12453fvTCps853rDOC/yXtvuLydIXGO76cXYWqr+pLEkpKeBU90zp1psXt8J04 L7H7xyvFusL/Kx/3F3wr/jJhmXS+37k6m0glluKMREMt5qLiRABjAPndsAIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The divider and mux register offsets and bits are different on Exynos7 from the older SoCs. Add new pre/post rate change callbacks for Exynos7 to handle these differences. To do this: - Add a new exynos_cpuclk_soc_data structure that will hold the SoC-specific pre/post rate change call-backs - Modify exynos_register_cpu_clock() prototype to include a node pointer Signed-off-by: Abhilash Kesavan --- drivers/clk/samsung/clk-cpu.c | 130 +++++++++++++++++++++++++++++++++- drivers/clk/samsung/clk-cpu.h | 33 ++++++++- drivers/clk/samsung/clk-exynos4.c | 2 +- drivers/clk/samsung/clk-exynos5250.c | 2 +- drivers/clk/samsung/clk-exynos5420.c | 4 +- 5 files changed, 163 insertions(+), 8 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 009a21b..6c00802 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -51,6 +51,13 @@ #define DIV_MASK_ALL 0xffffffff #define MUX_MASK 7 +#define EXYNOS7_SRC_CPU 0x208 +#define EXYNOS7_STAT_CPU 0x408 +#define EXYNOS7_DIV_CPU0 0x600 +#define EXYNOS7_DIV_CPU1 0x604 +#define EXYNOS7_DIV_STAT_CPU0 0x700 +#define EXYNOS7_DIV_STAT_CPU1 0x704 + /* * Helper function to wait until divider(s) have stabilized after the divider * value has changed. @@ -128,6 +135,88 @@ static void exynos_set_safe_div(void __iomem *base, unsigned long div, wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask); } +static void exynos7_set_safe_div(void __iomem *base, unsigned long div, + unsigned long mask) +{ + unsigned long div0; + + div0 = readl(base + EXYNOS7_DIV_CPU0); + div0 = (div0 & ~mask) | (div & mask); + writel(div0, base + EXYNOS7_DIV_CPU0); + wait_until_divider_stable(base + EXYNOS7_DIV_STAT_CPU0, mask); +} + +/* Exynos7 handler for pre-rate change notification from parent clock */ +static int exynos7_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, + struct exynos_cpuclk *cpuclk, void __iomem *base) +{ + const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; + unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent); + unsigned long alt_div = 0, alt_div_mask = DIV_MASK; + unsigned long div0, div1 = 0, mux_reg; + + /* find out the divider values to use for clock data */ + while ((cfg_data->prate * 1000) != ndata->new_rate) { + if (cfg_data->prate == 0) + return -EINVAL; + cfg_data++; + } + + spin_lock(cpuclk->lock); + + /* + * If the new and old parent clock speed is less than the clock speed + * of the alternate parent, then it should be ensured that at no point + * the armclk speed is more than the old_prate until the dividers are + * set. + */ + div0 = cfg_data->div0; + if (alt_prate > ndata->old_rate) { + alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1; + WARN_ON(alt_div >= MAX_DIV); + + exynos7_set_safe_div(base, alt_div, alt_div_mask); + div0 |= alt_div; + } + + /* select mout_bus0_pll_atlas as the alternate parent */ + mux_reg = readl(base + EXYNOS7_SRC_CPU); + writel(mux_reg | (1 << 0), base + EXYNOS7_SRC_CPU); + wait_until_mux_stable(base + EXYNOS7_STAT_CPU, 0, 1); + + /* alternate parent is active now. set the dividers */ + writel(div0, base + EXYNOS7_DIV_CPU0); + wait_until_divider_stable(base + EXYNOS7_DIV_STAT_CPU0, DIV_MASK_ALL); + + if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) { + writel(div1, base + EXYNOS7_DIV_CPU1); + wait_until_divider_stable(base + EXYNOS7_DIV_STAT_CPU1, + DIV_MASK_ALL); + } + + spin_unlock(cpuclk->lock); + return 0; +} + +/* Exynos7 handler for post-rate change notification from parent clock */ +static int exynos7_cpuclk_post_rate_change(struct clk_notifier_data *ndata, + struct exynos_cpuclk *cpuclk, void __iomem *base) +{ + unsigned long div = 0, div_mask = DIV_MASK; + unsigned long mux_reg; + + spin_lock(cpuclk->lock); + + /* select mout_atlas_pll as the alternate parent */ + mux_reg = readl(base + EXYNOS7_SRC_CPU); + writel(mux_reg & ~(1 << 0), base + EXYNOS7_SRC_CPU); + wait_until_mux_stable(base + EXYNOS7_STAT_CPU, 0, 0); + + exynos7_set_safe_div(base, div, div_mask); + spin_unlock(cpuclk->lock); + return 0; +} + /* handler for pre-rate change notification from parent clock */ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk, void __iomem *base) @@ -248,25 +337,58 @@ static int exynos_cpuclk_notifier_cb(struct notifier_block *nb, base = cpuclk->ctrl_base; if (event == PRE_RATE_CHANGE) - err = exynos_cpuclk_pre_rate_change(ndata, cpuclk, base); + err = cpuclk->pre_rate_cb(ndata, cpuclk, base); else if (event == POST_RATE_CHANGE) - err = exynos_cpuclk_post_rate_change(ndata, cpuclk, base); + err = cpuclk->post_rate_cb(ndata, cpuclk, base); return notifier_from_errno(err); } +static const struct exynos_cpuclk_soc_data e4210_clk_soc_data __initconst = { + .pre_rate_cb = exynos_cpuclk_pre_rate_change, + .post_rate_cb = exynos_cpuclk_post_rate_change, +}; + +static const struct exynos_cpuclk_soc_data e7_clk_soc_data __initconst = { + .pre_rate_cb = exynos7_cpuclk_pre_rate_change, + .post_rate_cb = exynos7_cpuclk_post_rate_change, +}; + +static const struct of_device_id exynos_cpuclk_ids[] __initconst = { + { .compatible = "samsung,exynos4210-clock", + .data = &e4210_clk_soc_data, }, + { .compatible = "samsung,exynos5250-clock", + .data = &e4210_clk_soc_data, }, + { .compatible = "samsung,exynos5420-clock", + .data = &e4210_clk_soc_data, }, + { .compatible = "samsung,exynos7-clock-atlas", + .data = &e7_clk_soc_data, }, + { }, +}; + /* helper function to register a CPU clock */ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, unsigned int lookup_id, const char *name, const char *parent, const char *alt_parent, unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg, - unsigned long num_cfgs, unsigned long flags) + unsigned long num_cfgs, unsigned long flags, + struct device_node *np) { + const struct of_device_id *match; + const struct exynos_cpuclk_soc_data *data = NULL; struct exynos_cpuclk *cpuclk; struct clk_init_data init; struct clk *clk; int ret = 0; + if (!np) + return -EINVAL; + + match = of_match_node(exynos_cpuclk_ids, np); + if (!match) + return -EINVAL; + data = match->data; + cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); if (!cpuclk) return -ENOMEM; @@ -281,6 +403,8 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, cpuclk->ctrl_base = ctx->reg_base + offset; cpuclk->lock = &ctx->lock; cpuclk->flags = flags; + cpuclk->pre_rate_cb = data->pre_rate_cb; + cpuclk->post_rate_cb = data->post_rate_cb; cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb; cpuclk->alt_parent = __clk_lookup(alt_parent); diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index 42e1905..24e844e 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -60,6 +60,10 @@ struct exynos_cpuclk_cfg_data { * @num_cfgs: number of array elements in @cfg array. * @clk_nb: clock notifier registered for changes in clock speed of the * primary parent clock. + * @pre_rate_cb: callback function to handle PRE_RATE_CHANGE notification + * of the primary parent clock. + * @post_rate_cb: callback function to handle POST_RATE_CHANGE notification + * of the primary parent clock. * @flags: configuration flags for the CPU clock. * * This structure holds information required for programming the CPU clock for @@ -73,6 +77,12 @@ struct exynos_cpuclk { const struct exynos_cpuclk_cfg_data *cfg; const unsigned long num_cfgs; struct notifier_block clk_nb; + int (*pre_rate_cb)(struct clk_notifier_data *, + struct exynos_cpuclk *, + void __iomem *base); + int (*post_rate_cb)(struct clk_notifier_data *, + struct exynos_cpuclk *, + void __iomem *base); unsigned long flags; /* The CPU clock registers has DIV1 configuration register */ @@ -81,11 +91,32 @@ struct exynos_cpuclk { #define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1) }; +/** + * struct exynos_cpuclk_soc_data: soc specific data for cpu clocks. + * @pre_rate_cb: callback function to handle PRE_RATE_CHANGE notification + * of the primary parent clock. + * @post_rate_cb: callback function to handle POST_RATE_CHANGE notification + * of the primary parent clock. + * + * This structure provides SoC specific data for CPU clocks. Based on + * the compatible value of the clock controller node, the value of the + * fields in this structure can be populated. + */ +struct exynos_cpuclk_soc_data { + int (*pre_rate_cb)(struct clk_notifier_data *, + struct exynos_cpuclk *, + void __iomem *base); + int (*post_rate_cb)(struct clk_notifier_data *, + struct exynos_cpuclk *, + void __iomem *base); +}; + extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, unsigned int lookup_id, const char *name, const char *parent, const char *alt_parent, unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg, - unsigned long num_cfgs, unsigned long flags); + unsigned long num_cfgs, unsigned long flags, + struct device_node *np); #endif /* __SAMSUNG_CLK_CPU_H */ diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 3731fc7..a057a24 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1473,7 +1473,7 @@ static void __init exynos4_clk_init(struct device_node *np, exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", mout_core_p4210[0], mout_core_p4210[1], 0x14200, e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), - CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, np); } else { samsung_clk_register_mux(ctx, exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 1d958f1..56b4147b 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -824,7 +824,7 @@ static void __init exynos5250_clk_init(struct device_node *np) exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", mout_cpu_p[0], mout_cpu_p[1], 0x200, exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d), - CLK_CPU_HAS_DIV1); + CLK_CPU_HAS_DIV1, np); /* * Enable arm clock down (in idle) and set arm divider diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index fcf365d..a8c668d 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1358,10 +1358,10 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", mout_cpu_p[0], mout_cpu_p[1], 0x200, - exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0, np); exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", mout_kfc_p[0], mout_kfc_p[1], 0x28200, - exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0); + exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0, np); exynos5420_clk_sleep_init();