From patchwork Mon Jan 5 12:19:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 5567641 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8E996BF6C3 for ; Mon, 5 Jan 2015 12:21:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 32AE920172 for ; Mon, 5 Jan 2015 12:21:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3FF9820165 for ; Mon, 5 Jan 2015 12:21:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753936AbbAEMUx (ORCPT ); Mon, 5 Jan 2015 07:20:53 -0500 Received: from mailout4.w1.samsung.com ([210.118.77.14]:43476 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753606AbbAEMTX (ORCPT ); Mon, 5 Jan 2015 07:19:23 -0500 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NHP00ED3EEZX1B0@mailout4.w1.samsung.com>; Mon, 05 Jan 2015 12:23:23 +0000 (GMT) X-AuditID: cbfec7f4-b7f126d000001e9a-0d-54aa8149d930 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id D0.D8.07834.9418AA45; Mon, 05 Jan 2015 12:19:21 +0000 (GMT) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0NHP00AYXE7XH550@eusync2.samsung.com>; Mon, 05 Jan 2015 12:19:21 +0000 (GMT) From: Marek Szyprowski To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marek Szyprowski , Tomasz Figa , Kyungmin Park , linux-samsung-soc@vger.kernel.org, linux-omap@vger.kernel.org, Arnd Bergmann , Olof Johansson , Russell King - ARM Linux , Kukjin Kim , lauraa@codeaurora.org, linus.walleij@linaro.org, tony@atomide.com, drake@endlessm.com, loeliger@gmail.com, Mark Rutland , nm@ti.com, khilman@linaro.org Subject: [PATCH v11 7/9] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310 Date: Mon, 05 Jan 2015 13:19:06 +0100 Message-id: <1420460348-20302-8-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 In-reply-to: <1420460348-20302-1-git-send-email-m.szyprowski@samsung.com> References: <1420460348-20302-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRmVeSWpSXmKPExsVy+t/xK7qejatCDB7P1bT4O+kYu8Wj+Y+Z LXoXXGWz+Hp4BaPF2aY37BbbO2ewW0z5s5zJYtPja6wWl3fNYbOYvaSfxWLG+X1MFrcv81qc 276FxWLtkbvsFkuvX2SyePPjLJPFqeuf2SxW7frDaLH/ipeDsMeaeWsYPVqae9g8fv+axOjx 7eskFo/Lfb1MHou+Z3nsnHWX3ePOtT1sHpuX1HtcOdHE6tG3ZRWjx/Eb25k8Pm+SC+CN4rJJ Sc3JLEst0rdL4Mp4dmA/c8Fu8YoP314yNjCuE+5i5OSQEDCR+HnpKiOELSZx4d56ti5GLg4h gaWMEtNf/mKGcPqYJHZtusAGUsUmYCjR9bYLzBYRcJP4t+4QWAezwDQWiU1HzjODJIQFwiU2 PVkFZrMIqEo87LjJDmLzCnhIfFp0ixVinZzE/5crmEBsTgFPiaV794HVCAHVnLm1ln0CI+8C RoZVjKKppckFxUnpuYZ6xYm5xaV56XrJ+bmbGCGR8WUH4+JjVocYBTgYlXh4PU6sDBFiTSwr rsw9xCjBwawkwvsqfVWIEG9KYmVValF+fFFpTmrxIUYmDk6pBsZ5L3gaf9k0VHSc070kb8J/ uupfCcvlhDu1D83PJAjU108znXn+jUbTJJ/CxseuUp8e/me7OHOvcUXOU/e83HNXVh1xnCh6 bGXsmxsBnLI3VqZmljdaXRFIyuje+Erz5UIlzdm55o8kOlSYFrD0sTg6eCzYmrA/vOLOQa5v Duv2PWq4YiM/x0iJpTgj0VCLuag4EQBX+hJbagIAAA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tomasz Figa Exynos4 SoCs equipped with an L2C-310 cache controller and running under secure firmware require certain registers of aforementioned IP to be accessed only from secure mode. This means that SMC calls are required for certain register writes. To handle this, an implementation of .write_sec and .configure callbacks is provided by this patch. Signed-off-by: Tomasz Figa [added comment and reworked unconditional call to SMC_CMD_L2X0INVALL] Signed-off-by: Marek Szyprowski Acked-by: Arnd Bergmann Acked-by: Kukjin Kim --- arch/arm/mach-exynos/firmware.c | 50 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 766f57d2f029..dc5ae53aa317 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -136,6 +137,43 @@ static const struct firmware_ops exynos_firmware_ops = { .resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL, }; +static void exynos_l2_write_sec(unsigned long val, unsigned reg) +{ + static int l2cache_enabled; + + switch (reg) { + case L2X0_CTRL: + if (val & L2X0_CTRL_EN) { + /* + * Before the cache can be enabled, due to firmware + * design, SMC_CMD_L2X0INVALL must be called. + */ + if (!l2cache_enabled) { + exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); + l2cache_enabled = 1; + } + } else { + l2cache_enabled = 0; + } + exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0); + break; + + case L2X0_DEBUG_CTRL: + exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0); + break; + + default: + WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg); + } +} + +static void exynos_l2_configure(const struct l2x0_regs *regs) +{ + exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency, + regs->prefetch_ctrl); + exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0); +} + void __init exynos_firmware_init(void) { struct device_node *nd; @@ -155,4 +193,16 @@ void __init exynos_firmware_init(void) pr_info("Running under secure firmware.\n"); register_firmware_ops(&exynos_firmware_ops); + + /* + * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310), + * running under secure firmware, require certain registers of L2 + * cache controller to be written in secure mode. Here .write_sec + * callback is provided to perform necessary SMC calls. + */ + if (IS_ENABLED(CONFIG_CACHE_L2X0) + && read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { + outer_cache.write_sec = exynos_l2_write_sec; + outer_cache.configure = exynos_l2_configure; + } }