From patchwork Wed Jan 21 16:07:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 5679031 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B0D23C058D for ; Wed, 21 Jan 2015 16:07:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DCF97204DF for ; Wed, 21 Jan 2015 16:07:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1A6FE201BB for ; Wed, 21 Jan 2015 16:07:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753092AbbAUQHp (ORCPT ); Wed, 21 Jan 2015 11:07:45 -0500 Received: from mail-lb0-f179.google.com ([209.85.217.179]:65112 "EHLO mail-lb0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752086AbbAUQHn (ORCPT ); Wed, 21 Jan 2015 11:07:43 -0500 Received: by mail-lb0-f179.google.com with SMTP id z11so40110158lbi.10; Wed, 21 Jan 2015 08:07:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=eAu1d41c3ptFBO/bd6EhNYVt1iX2/jvgKiaNrw3YGiY=; b=0nnbo2bp1D46KfQjxhdmAMo9CQyBgCFm8cQ7GOhBJzpFxUmuUOydRtHDXDbMshNumd Tc/kW/erGxo+dNcUHn+VZmILC235Vmtk6LLWsR5v4w4WmUX3I4WJot+T1ggCGRp/lVpJ nBy5JAjh8MhuotPue8x08eUFbLEAXOe0fpcKHecGC4XmbUWkTIRmeBbJJJm6tkuXQk5y OirQ0iiEy9WY6vYtn9V8uFYpCwl6TC//QOwCc4Rh0XwmgkPCJcFPkH8hh/+H7jeil8Vl k6rhkkbNjW7uSH6KenT3kP/sutZO2d3hSx4VgMuTRoKubZ2hxmQmr/m6kjwPYaXEZzx/ M2jQ== X-Received: by 10.152.44.193 with SMTP id g1mr24061408lam.15.1421856461831; Wed, 21 Jan 2015 08:07:41 -0800 (PST) Received: from localhost.localdomain (ppp95-165-114-106.pppoe.spdop.ru. [95.165.114.106]) by mx.google.com with ESMTPSA id ki4sm5620057lac.1.2015.01.21.08.07.40 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Jan 2015 08:07:41 -0800 (PST) From: Dmitry Osipenko To: digetx@gmail.com, Russell King , Tomasz Figa , Kukjin Kim , Shawn Guo , Sascha Hauer , Joseph Lo , Stephen Warren , Peter De Schrijver Cc: Ben Dooks , Bob Mottram , linux-tegra@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2] ARM: l2c: Maintain CPU endianness for early resume function Date: Wed, 21 Jan 2015 19:07:19 +0300 Message-Id: <1421856440-28097-1-git-send-email-digetx@gmail.com> X-Mailer: git-send-email 2.2.1 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In big endian CPU mode l2x0_saved_regs structure stores registers values in BE format. In order to maintain BE CPU mode, these values and immediate constants must be converted back to LE format before writing them to cache controller. Signed-off-by: Dmitry Osipenko --- V2: no code change, fixed patch numbering, extended mail recipients list arch/arm/mm/l2c-l2x0-resume.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mm/l2c-l2x0-resume.S b/arch/arm/mm/l2c-l2x0-resume.S index fda415e..9f99c7e 100644 --- a/arch/arm/mm/l2c-l2x0-resume.S +++ b/arch/arm/mm/l2c-l2x0-resume.S @@ -30,6 +30,15 @@ ENTRY(l2c310_early_resume) teq r1, #0 reteq lr + @ Reverse for big endian kernel +ARM_BE8(rev r2, r2) +ARM_BE8(rev r3, r3) +ARM_BE8(rev r4, r4) +ARM_BE8(rev r5, r5) +ARM_BE8(rev r6, r6) +ARM_BE8(rev r7, r7) +ARM_BE8(rev r8, r8) + @ The prefetch and power control registers are revision dependent @ and can be written whether or not the L2 cache is enabled ldr r0, [r1, #L2X0_CACHE_ID] @@ -51,6 +60,7 @@ ENTRY(l2c310_early_resume) str r2, [r1, #L2X0_AUX_CTRL] mov r9, #L2X0_CTRL_EN +ARM_BE8(rev r9, r9) str r9, [r1, #L2X0_CTRL] ret lr ENDPROC(l2c310_early_resume)