From patchwork Thu Jan 29 02:41:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 5735801 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E96499F38B for ; Thu, 29 Jan 2015 02:50:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0F85420121 for ; Thu, 29 Jan 2015 02:50:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 50BFE20219 for ; Thu, 29 Jan 2015 02:50:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1762979AbbA2Cuc (ORCPT ); Wed, 28 Jan 2015 21:50:32 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:27372 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760620AbbA2Cu1 (ORCPT ); Wed, 28 Jan 2015 21:50:27 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NIX00F3E3W11E90@mailout1.samsung.com>; Thu, 29 Jan 2015 11:50:25 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.48]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 13.5C.18484.0FF99C45; Thu, 29 Jan 2015 11:50:25 +0900 (KST) X-AuditID: cbfee68f-f791c6d000004834-10-54c99ff0fccf Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 09.88.20081.0FF99C45; Thu, 29 Jan 2015 11:50:24 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NIX00A433V4TFF0@mmp1.samsung.com>; Thu, 29 Jan 2015 11:50:24 +0900 (KST) From: Alim Akhtar To: linux-mmc@vger.kernel.org Cc: chris@printf.net, ulf.hansson@linaro.org, jh80.chung@samsung.com, tgih.jun@samsung.com, dianders@chromium.org, alim.akhtar@gmail.com, kgene@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, a.kesavan@samsung.com, alim.akhtar@samsung.com Subject: [PATCH V5 2/2] ARM: dts: Add HS400 support for exynos5420 and exynos5800 Date: Thu, 29 Jan 2015 08:11:58 +0530 Message-id: <1422499318-13726-3-git-send-email-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.2.0 In-reply-to: <1422499318-13726-1-git-send-email-alim.akhtar@samsung.com> References: <1422499318-13726-1-git-send-email-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpjkeLIzCtJLcpLzFFi42I5/e+Zge7H+SdDDD7/ZbZ4vGYxk8XSW9UW D+ZtY7OYcHk7o8X8I+dYLc4uO8hmceNXG6tF/+PXzBabHl9jtTjyv5/RYsb5fUwWH+5fZLY4 vjbcgddjdsNFFo+ds+6ye2xa1cnmcefaHjaPzUvqPW68Wsjk0bdlFaPH501yARxRXDYpqTmZ ZalF+nYJXBkzDu9iKXguVdH69ix7A+MxsS5GTg4JAROJt4c3sULYYhIX7q1n62Lk4hASWMYo saJ9CyNM0ZZ73YwQiUWMEsderIaqmsAksXLDfyaQKjYBbYm707eA2SICshI//1xgA7GZBbYz SWyd7gJiCwsES0w+t4odxGYRUJW4eOghM4jNK+AucfvNH2aIbXISW249AqvhFPCQ+H1vK9hM IaCat20nWUEWSwhcY5c4tegAM8QgAYlvkw+xdDFyACVkJTYdgJojKXFwxQ2WCYzCCxgZVjGK phYkFxQnpRcZ6xUn5haX5qXrJefnbmKERE//Dsa7B6wPMQpwMCrx8CY0ngwRYk0sK67MPcRo CrRhIrOUaHI+MEbzSuINjc2MLExNTI2NzC3NlMR5F0r9DBYSSE8sSc1OTS1ILYovKs1JLT7E yMTBKdXAyFT8fpGUnbuYfF2g+F6+NqsVqkw8RttWxi/p1dukM5FNgcnIukxy1scVjJ+OSCir mp+X+x6ikxg/V3ITg0eJ7YE3elaZkqer+Jm6DA0/nbYUezej1kfF+W1jhluw0L2g2tuyoTcf urkt8bsVXhVjMElpjYF4hWbqDIury5MS4xYLfwzJmanEUpyRaKjFXFScCACGeK6cmQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrAIsWRmVeSWpSXmKPExsVy+t9jAd0P80+GGHSfsbR4vGYxk8XSW9UW D+ZtY7OYcHk7o8X8I+dYLc4uO8hmceNXG6tF/+PXzBabHl9jtTjyv5/RYsb5fUwWH+5fZLY4 vjbcgddjdsNFFo+ds+6ye2xa1cnmcefaHjaPzUvqPW68Wsjk0bdlFaPH501yARxRDYw2GamJ KalFCql5yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUAXKymUJeaUAoUC EouLlfTtME0IDXHTtYBpjND1DQmC6zEyQAMJ6xgzZhzexVLwXKqi9e1Z9gbGY2JdjJwcEgIm ElvudTNC2GISF+6tZ+ti5OIQEljEKHHsxWooZwKTxMoN/5lAqtgEtCXuTt8CZosIyEr8/HOB DcRmFtjOJLF1uguILSwQLDH53Cp2EJtFQFXi4qGHzCA2r4C7xO03f5ghtslJbLn1CKyGU8BD 4ve9rWAzhYBq3radZJ3AyLuAkWEVo2hqQXJBcVJ6rqFecWJucWleul5yfu4mRnBsPpPawbiy weIQowAHoxIPL0f9yRAh1sSy4srcQ4wSHMxKIrzXm4FCvCmJlVWpRfnxRaU5qcWHGE2BrprI LCWanA9MG3kl8YbGJmZGlkZmFkYm5uZK4rxK9m0hQgLpiSWp2ampBalFMH1MHJxSDYwlrEwc Yb2/4t49FHpmt1Lr6aTsLXse8peWvwmOdvrcEH7z06Z/z190c/+ctedycbH0SgvBQ1ZsWWlP cwq/7ox+L6hy8t7MB9dO3uoUvRGidkdx0k5Vy+nuQioy60KmLQ/vdhZ4u+CD5/9lYbe8pxYX 3bwwR1O07JBL1kqzidtW+h5tjlJ6f0ZHiaU4I9FQi7moOBEAYPkFVOMCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Seungwon Jeon HS400 timing values are added for SMDK5420, exynos5420-peach-pit and exynos5800-peach-pi boards. This also adds RCLK GPIO line, this gpio should be in pull-down state. This also enables HS400 on peach-pi and this updates the clock frequency to 800MHz to be set as input clock to controller. Signed-off-by: Seungwon Jeon Signed-off-by: Alim Akhtar [Alim: addressed review comments] Acked-by: Jaehoon Chung --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +++- arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 7 +++++++ arch/arm/boot/dts/exynos5420-smdk5420.dts | 4 +++- arch/arm/boot/dts/exynos5800-peach-pi.dts | 7 +++++-- 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 9a050e1..f7a44a4 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -569,8 +569,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; }; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index ba686e4..8b15316 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -201,6 +201,13 @@ samsung,pin-drv = <3>; }; + sd0_rclk: sd0-rclk { + samsung,pins = "gpc0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + sd1_cmd: sd1-cmd { samsung,pins = "gpc1-1"; samsung,pin-function = <2>; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 8be3d7b..2078a1f 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -80,8 +80,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; cap-mmc-highspeed; }; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index e8fdda8..96f0d61 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -550,15 +550,18 @@ num-slots = <1>; broken-cd; mmc-hs200-1_8v; + mmc-hs400-1_8v; cap-mmc-highspeed; non-removable; card-detect-delay = <200>; - clock-frequency = <400000000>; + clock-frequency = <800000000>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; };