| Message ID | 1422882074-19758-2-git-send-email-cw00.choi@samsung.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
Hi Chanwoo, On 02/02/15 14:01, Chanwoo Choi wrote: > This patch adds devicetree binding document for Exynos5433 SoC system clock > controller. > > Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> > Cc: Tomasz Figa <tomasz.figa@gmail.com> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > Acked-by: Inki Dae <inki.dae@samsung.com> > --- > .../devicetree/bindings/clock/exynos5433-clock.txt | 258 +++++++++++++++++++++ > 1 file changed, 258 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt > > diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt > new file mode 100644 > index 0000000..2d7a723 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt > @@ -0,0 +1,258 @@ > +* Samsung Exynos5433 CMU (Clock Management Units) > + > +The Exynos5433 clock controller generates and supplies clock to various > +controllers within the Exynos5433 SoC. > + > +Required Properties: > + > +- compatible: should be one of the following. > + - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP > + which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS > + domains and bus clocks. > + - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF > + which generates clocks for LLI (Low Latency Interface) IP. > + - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF > + which generates clocks for DRAM Memory Controller domain. > + - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC > + which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. > + - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS > + which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. > + - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS > + which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. > + - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D > + which generates clocks for G2D/MDMA IPs. > + - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP > + which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. > + - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD > + which generates clocks for Cortex-A5/BUS/AUDIO clocks. > + - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" > + and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS > + which generates global data buses clock and global peripheral buses clock. > + - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D > + which generates clocks for 3D Graphics Engine IP. > + - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL > + which generates clocks for GSCALER IPs. > + > +- reg: physical base address of the controller and length of memory mapped > + region. > + > +- #clock-cells: should be 1. Thanks for addressing my comments! It looks almost good enough, can you just please also add clocks, clock-names to the list of required properties ? I guess it's sufficient to mention that these properties should contain values as listed in the examples below per each CMU. This also applies to you following series of 9 patches. > + > +Each clock is assigned an identifier and client nodes can use this identifier > +to specify the clock which they consume. > + > +All available clocks are defined as preprocessor macros in > +dt-bindings/clock/exynos5433.h header and can be used in device > +tree sources. > + > +Example 1: Examples of 'oscclk' source clock node are listed below. > + > + xxti: xxti { > + compatible = "fixed-clock"; > + clock-output-names = "oscclk"; > + #clock-cells = <0>; > + }; > + > +Example 2: Examples of clock controller nodes are listed below. > + > + cmu_top: clock-controller@0x10030000 { > + compatible = "samsung,exynos5433-cmu-top"; > + reg = <0x10030000 0x0c04>; > + #clock-cells = <1>; > + > + clock-names = "oscclk", > + "sclk_mphy_pll", > + "sclk_mfc_pll", > + "sclk_bus_pll"; > + clocks = <&xxti>, > + <&cmu_cpif CLK_SCLK_MPHY_PLL>, > + <&cmu_mif CLK_SCLK_MFC_PLL>, > + <&cmu_mif CLK_SCLK_BUS_PLL>; > + }; > + cmu_gscl: clock-controller@0x13cf0000 { > + compatible = "samsung,exynos5433-cmu-gscl"; > + reg = <0x13cf0000 0x0b10>; > + #clock-cells = <1>; > + > + clock-names = "oscclk", > + "aclk_gscl_111", > + "aclk_gscl_333"; > + clocks = <&xxti>, > + <&cmu_top CLK_ACLK_GSCL_111>, > + <&cmu_top CLK_ACLK_GSCL_333>; > + }; > + > +Example 3: UART controller node that consumes the clock generated by the clock > + controller. > + > + serial_0: serial@14C10000 { > + compatible = "samsung,exynos5433-uart"; > + reg = <0x14C10000 0x100>; > + interrupts = <0 421 0>; > + clocks = <&cmu_peric CLK_PCLK_UART0>, > + <&cmu_peric CLK_SCLK_UART0>; > + clock-names = "uart", "clk_uart_baud0"; > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_bus>; > + status = "disabled"; > + }; > + > +Example 4: SPI controller node that consumes the clock generated by the clock > + controller. This fourth example doesn't look like it adds significant value, I'd say it can be removed. > + spi_0: spi@14d20000 { > + compatible = "samsung,exynos7-spi"; > + reg = <0x14d20000 0x100>; > + interrupts = <0 432 0>; > + dmas = <&pdma0 9>, <&pdma0 8>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&cmu_peric CLK_PCLK_SPI0>, > + <&cmu_top CLK_SCLK_SPI0_PERIC>; > + clock-names = "spi", "spi_busclk0"; > + samsung,spi-src-clk = <0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&spi0_bus>; > + status = "disabled"; > + }; > Also please don't forget to Cc devicetree@vger.kernel.org next time. -- Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Sylwester, On 02/02/2015 10:55 PM, Sylwester Nawrocki wrote: > Hi Chanwoo, > > On 02/02/15 14:01, Chanwoo Choi wrote: >> This patch adds devicetree binding document for Exynos5433 SoC system clock >> controller. >> >> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> >> Cc: Tomasz Figa <tomasz.figa@gmail.com> >> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> >> Acked-by: Inki Dae <inki.dae@samsung.com> >> --- >> .../devicetree/bindings/clock/exynos5433-clock.txt | 258 +++++++++++++++++++++ >> 1 file changed, 258 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt >> >> diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt >> new file mode 100644 >> index 0000000..2d7a723 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt >> @@ -0,0 +1,258 @@ >> +* Samsung Exynos5433 CMU (Clock Management Units) >> + >> +The Exynos5433 clock controller generates and supplies clock to various >> +controllers within the Exynos5433 SoC. >> + >> +Required Properties: >> + >> +- compatible: should be one of the following. >> + - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP >> + which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS >> + domains and bus clocks. >> + - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF >> + which generates clocks for LLI (Low Latency Interface) IP. >> + - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF >> + which generates clocks for DRAM Memory Controller domain. >> + - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC >> + which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. >> + - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS >> + which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. >> + - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS >> + which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. >> + - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D >> + which generates clocks for G2D/MDMA IPs. >> + - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP >> + which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. >> + - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD >> + which generates clocks for Cortex-A5/BUS/AUDIO clocks. >> + - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" >> + and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS >> + which generates global data buses clock and global peripheral buses clock. >> + - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D >> + which generates clocks for 3D Graphics Engine IP. >> + - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL >> + which generates clocks for GSCALER IPs. >> + >> +- reg: physical base address of the controller and length of memory mapped >> + region. >> + >> +- #clock-cells: should be 1. > > Thanks for addressing my comments! It looks almost good enough, can you > just please also add clocks, clock-names to the list of required properties ? > I guess it's sufficient to mention that these properties should contain > values as listed in the examples below per each CMU. > This also applies to you following series of 9 patches. OK, I'll add more following information: I'll send only patch1 with following information. + - clocks: list of clock identifiers which are fed as the input to + the given clock controller. Please refer the next section to + find the input clocks for a given controller. + +- clock-names: list of names of clocks which are fed as the input + to the given clock controller. + + Input clocks for top clock controller: + - oscclk + - sclk_mphy_pll + - sclk_mfc_pll + - sclk_bus_pll + + Input clocks for cpif clock controller: + - oscclk + + Input clocks for mif clock controller: + - oscclk + - sclk_mphy_pll + + Input clocks for fsys clock controller: + - oscclk + - sclk_ufs_mphy + - div_aclk_fsys_200 + - sclk_pcie_100_fsys + - sclk_ufsunipro_fsys + - sclk_mmc2_fsys + - sclk_mmc1_fsys + - sclk_mmc0_fsys + - sclk_usbhost30_fsys + - sclk_usbdrd30_fsys + + Input clocks for g2d clock controller: + - oscclk + - aclk_g2d_266 + - aclk_g2d_400 + + Input clocks for disp clock controller: + - oscclk + - sclk_dsim1_disp + - sclk_dsim0_disp + - sclk_dsd_disp + - sclk_decon_tv_eclk_disp + - sclk_decon_vclk_disp + - sclk_decon_eclk_disp + - sclk_decon_tv_vclk_disp + - aclk_disp_333 + + Input clocks for bus0 clock controller: + - aclk_bus0_400 + + Input clocks for bus1 clock controller: + - aclk_bus1_400 + + Input clocks for bus2 clock controller: + - oscclk + - aclk_bus2_400 + + Input clocks for g3d clock controller: + - oscclk + - aclk_g3d_400 + + Input clocks for gscl clock controller: + - oscclk + - aclk_gscl_111 + - aclk_gscl_333 > >> + >> +Each clock is assigned an identifier and client nodes can use this identifier >> +to specify the clock which they consume. >> + >> +All available clocks are defined as preprocessor macros in >> +dt-bindings/clock/exynos5433.h header and can be used in device >> +tree sources. >> + >> +Example 1: Examples of 'oscclk' source clock node are listed below. >> + >> + xxti: xxti { >> + compatible = "fixed-clock"; >> + clock-output-names = "oscclk"; >> + #clock-cells = <0>; >> + }; >> + >> +Example 2: Examples of clock controller nodes are listed below. >> + >> + cmu_top: clock-controller@0x10030000 { >> + compatible = "samsung,exynos5433-cmu-top"; >> + reg = <0x10030000 0x0c04>; >> + #clock-cells = <1>; >> + >> + clock-names = "oscclk", >> + "sclk_mphy_pll", >> + "sclk_mfc_pll", >> + "sclk_bus_pll"; >> + clocks = <&xxti>, >> + <&cmu_cpif CLK_SCLK_MPHY_PLL>, >> + <&cmu_mif CLK_SCLK_MFC_PLL>, >> + <&cmu_mif CLK_SCLK_BUS_PLL>; >> + }; > >> + cmu_gscl: clock-controller@0x13cf0000 { >> + compatible = "samsung,exynos5433-cmu-gscl"; >> + reg = <0x13cf0000 0x0b10>; >> + #clock-cells = <1>; >> + >> + clock-names = "oscclk", >> + "aclk_gscl_111", >> + "aclk_gscl_333"; >> + clocks = <&xxti>, >> + <&cmu_top CLK_ACLK_GSCL_111>, >> + <&cmu_top CLK_ACLK_GSCL_333>; >> + }; >> + >> +Example 3: UART controller node that consumes the clock generated by the clock >> + controller. >> + >> + serial_0: serial@14C10000 { >> + compatible = "samsung,exynos5433-uart"; >> + reg = <0x14C10000 0x100>; >> + interrupts = <0 421 0>; >> + clocks = <&cmu_peric CLK_PCLK_UART0>, >> + <&cmu_peric CLK_SCLK_UART0>; >> + clock-names = "uart", "clk_uart_baud0"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&uart0_bus>; >> + status = "disabled"; >> + }; >> + >> +Example 4: SPI controller node that consumes the clock generated by the clock >> + controller. > > This fourth example doesn't look like it adds significant value, I'd say it > can be removed. OK, I'll merge it. > >> + spi_0: spi@14d20000 { >> + compatible = "samsung,exynos7-spi"; >> + reg = <0x14d20000 0x100>; >> + interrupts = <0 432 0>; >> + dmas = <&pdma0 9>, <&pdma0 8>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&cmu_peric CLK_PCLK_SPI0>, >> + <&cmu_top CLK_SCLK_SPI0_PERIC>; >> + clock-names = "spi", "spi_busclk0"; >> + samsung,spi-src-clk = <0>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&spi0_bus>; >> + status = "disabled"; >> + }; >> > > Also please don't forget to Cc devicetree@vger.kernel.org next time. OK. Thanks, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 02/02/15 15:08, Chanwoo Choi wrote: > OK, I'll add more following information: > I'll send only patch1 with following information. > > + - clocks: list of clock identifiers which are fed as the input to > + the given clock controller. Please refer the next section to > + find the input clocks for a given controller. > + - clock-names: list of names of clocks which are fed as the input > + to the given clock controller. > + Perhaps: + - clocks: list of the clock controller input clock identifiers, from common clock bindings. Please refer the next section to find the input clocks for a given controller. +- clock-names: list of the clock controller input clock names, as described in clock-bindings.txt. ? It's fine to resend just updated first patch from each series.
Hi Sylwester, On Mon, Feb 2, 2015 at 11:40 PM, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote: > On 02/02/15 15:08, Chanwoo Choi wrote: > >> OK, I'll add more following information: >> I'll send only patch1 with following information. >> >> + - clocks: list of clock identifiers which are fed as the input to >> + the given clock controller. Please refer the next section to >> + find the input clocks for a given controller. >> + - clock-names: list of names of clocks which are fed as the input >> + to the given clock controller. >> + > > Perhaps: > > + - clocks: list of the clock controller input clock identifiers, > from common clock bindings. Please refer the next section > to find the input clocks for a given controller. > > +- clock-names: list of the clock controller input clock names, > as described in clock-bindings.txt. > > ? > It's fine to resend just updated first patch from each series. OK, I'll modify the comment of 'clocks' and 'clock-names' and send only first patch. I have a question. Do you prefer to add the list of input clocks for each clock domain as following? Or it is not necessary? + Input clocks for top clock controller: + - oscclk + - sclk_mphy_pll + - sclk_mfc_pll + - sclk_bus_pll Thanks, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Chanwoo, On 02/02/15 16:51, Chanwoo Choi wrote: > On Mon, Feb 2, 2015 at 11:40 PM, Sylwester Nawrocki > <s.nawrocki@samsung.com> wrote: >> > On 02/02/15 15:08, Chanwoo Choi wrote: >> > >>> >> OK, I'll add more following information: >>> >> I'll send only patch1 with following information. >>> >> >>> >> + - clocks: list of clock identifiers which are fed as the input to >>> >> + the given clock controller. Please refer the next section to >>> >> + find the input clocks for a given controller. >>> >> + - clock-names: list of names of clocks which are fed as the input >>> >> + to the given clock controller. >>> >> + >> > >> > Perhaps: >> > >> > + - clocks: list of the clock controller input clock identifiers, >> > from common clock bindings. Please refer the next section >> > to find the input clocks for a given controller. >> > >> > +- clock-names: list of the clock controller input clock names, >> > as described in clock-bindings.txt. >> > >> > ? >> > It's fine to resend just updated first patch from each series. > OK, > I'll modify the comment of 'clocks' and 'clock-names' and send only first patch. > > I have a question. Do you prefer to add the list of input clocks for > each clock domain as following? > Or it is not necessary? > > + Input clocks for top clock controller: > + - oscclk > + - sclk_mphy_pll > + - sclk_mfc_pll > + - sclk_bus_pll We are supposed to document all required input clocks somehow, I would keep the list in such form. The (example) cmu nodes are also a good documentation IMHO, they also show clearly which cmu (block) given clock is sourced from. -- Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Sylwester, On Tue, Feb 3, 2015 at 1:25 AM, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote: > Hi Chanwoo, > > On 02/02/15 16:51, Chanwoo Choi wrote: >> On Mon, Feb 2, 2015 at 11:40 PM, Sylwester Nawrocki >> <s.nawrocki@samsung.com> wrote: >>> > On 02/02/15 15:08, Chanwoo Choi wrote: >>> > >>>> >> OK, I'll add more following information: >>>> >> I'll send only patch1 with following information. >>>> >> >>>> >> + - clocks: list of clock identifiers which are fed as the input to >>>> >> + the given clock controller. Please refer the next section to >>>> >> + find the input clocks for a given controller. >>>> >> + - clock-names: list of names of clocks which are fed as the input >>>> >> + to the given clock controller. >>>> >> + >>> > >>> > Perhaps: >>> > >>> > + - clocks: list of the clock controller input clock identifiers, >>> > from common clock bindings. Please refer the next section >>> > to find the input clocks for a given controller. >>> > >>> > +- clock-names: list of the clock controller input clock names, >>> > as described in clock-bindings.txt. >>> > >>> > ? >>> > It's fine to resend just updated first patch from each series. >> OK, >> I'll modify the comment of 'clocks' and 'clock-names' and send only first patch. >> >> I have a question. Do you prefer to add the list of input clocks for >> each clock domain as following? >> Or it is not necessary? >> >> + Input clocks for top clock controller: >> + - oscclk >> + - sclk_mphy_pll >> + - sclk_mfc_pll >> + - sclk_bus_pll > > We are supposed to document all required input clocks somehow, I would > keep the list in such form. The (example) cmu nodes are also a good > documentation IMHO, they also show clearly which cmu (block) given clock > is sourced from. I agree that the binding document have to contain all required information. The binding document of exynos5433-clock will contain all input clocks for each clock domain. Also, I'll modify the description of 'clocks'/'clock-names' according to your comment and then I'll re-send only updated first patch for document. Thanks, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Sylwester, On 02/03/2015 01:44 AM, Chanwoo Choi wrote: > Hi Sylwester, > > On Tue, Feb 3, 2015 at 1:25 AM, Sylwester Nawrocki > <s.nawrocki@samsung.com> wrote: >> Hi Chanwoo, >> >> On 02/02/15 16:51, Chanwoo Choi wrote: >>> On Mon, Feb 2, 2015 at 11:40 PM, Sylwester Nawrocki >>> <s.nawrocki@samsung.com> wrote: >>>>> On 02/02/15 15:08, Chanwoo Choi wrote: >>>>> >>>>>>> OK, I'll add more following information: >>>>>>> I'll send only patch1 with following information. >>>>>>> >>>>>>> + - clocks: list of clock identifiers which are fed as the input to >>>>>>> + the given clock controller. Please refer the next section to >>>>>>> + find the input clocks for a given controller. >>>>>>> + - clock-names: list of names of clocks which are fed as the input >>>>>>> + to the given clock controller. >>>>>>> + >>>>> >>>>> Perhaps: >>>>> >>>>> + - clocks: list of the clock controller input clock identifiers, >>>>> from common clock bindings. Please refer the next section >>>>> to find the input clocks for a given controller. >>>>> >>>>> +- clock-names: list of the clock controller input clock names, >>>>> as described in clock-bindings.txt. >>>>> >>>>> ? >>>>> It's fine to resend just updated first patch from each series. >>> OK, >>> I'll modify the comment of 'clocks' and 'clock-names' and send only first patch. >>> >>> I have a question. Do you prefer to add the list of input clocks for >>> each clock domain as following? >>> Or it is not necessary? >>> >>> + Input clocks for top clock controller: >>> + - oscclk >>> + - sclk_mphy_pll >>> + - sclk_mfc_pll >>> + - sclk_bus_pll >> >> We are supposed to document all required input clocks somehow, I would >> keep the list in such form. The (example) cmu nodes are also a good >> documentation IMHO, they also show clearly which cmu (block) given clock >> is sourced from. > > I agree that the binding document have to contain all required information. > The binding document of exynos5433-clock will contain all input clocks for > each clock domain. Also, I'll modify the description of 'clocks'/'clock-names' > according to your comment and then I'll re-send only updated first > patch for document. I send only updated first patch[1] and will post new patch-set(v3) for remainings 9 patches with input clock information. [1] https://lkml.org/lkml/2015/2/2/761 - [PATCH v6] clk: samsung: exynos5433: Add binding document for Exynos5433 clock domains Thanks, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt new file mode 100644 index 0000000..2d7a723 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt @@ -0,0 +1,258 @@ +* Samsung Exynos5433 CMU (Clock Management Units) + +The Exynos5433 clock controller generates and supplies clock to various +controllers within the Exynos5433 SoC. + +Required Properties: + +- compatible: should be one of the following. + - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP + which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS + domains and bus clocks. + - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF + which generates clocks for LLI (Low Latency Interface) IP. + - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF + which generates clocks for DRAM Memory Controller domain. + - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC + which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. + - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS + which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. + - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS + which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. + - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D + which generates clocks for G2D/MDMA IPs. + - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP + which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. + - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD + which generates clocks for Cortex-A5/BUS/AUDIO clocks. + - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" + and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS + which generates global data buses clock and global peripheral buses clock. + - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D + which generates clocks for 3D Graphics Engine IP. + - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL + which generates clocks for GSCALER IPs. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos5433.h header and can be used in device +tree sources. + +Example 1: Examples of 'oscclk' source clock node are listed below. + + xxti: xxti { + compatible = "fixed-clock"; + clock-output-names = "oscclk"; + #clock-cells = <0>; + }; + +Example 2: Examples of clock controller nodes are listed below. + + cmu_top: clock-controller@0x10030000 { + compatible = "samsung,exynos5433-cmu-top"; + reg = <0x10030000 0x0c04>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_mphy_pll", + "sclk_mfc_pll", + "sclk_bus_pll"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_MPHY_PLL>, + <&cmu_mif CLK_SCLK_MFC_PLL>, + <&cmu_mif CLK_SCLK_BUS_PLL>; + }; + + cmu_cpif: clock-controller@0x10fc0000 { + compatible = "samsung,exynos5433-cmu-cpif"; + reg = <0x10fc0000 0x0c04>; + #clock-cells = <1>; + + clock-names = "oscclk"; + clocks = <&xxti>; + }; + + cmu_mif: clock-controller@0x105b0000 { + compatible = "samsung,exynos5433-cmu-mif"; + reg = <0x105b0000 0x100c>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_mphy_pll"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_MPHY_PLL>; + }; + + cmu_peric: clock-controller@0x14c80000 { + compatible = "samsung,exynos5433-cmu-peric"; + reg = <0x14c80000 0x0b08>; + #clock-cells = <1>; + }; + + cmu_peris: clock-controller@0x10040000 { + compatible = "samsung,exynos5433-cmu-peris"; + reg = <0x10040000 0x0b20>; + #clock-cells = <1>; + }; + + cmu_fsys: clock-controller@0x156e0000 { + compatible = "samsung,exynos5433-cmu-fsys"; + reg = <0x156e0000 0x0b04>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_ufs_mphy", + "div_aclk_fsys_200", + "sclk_pcie_100_fsys", + "sclk_ufsunipro_fsys", + "sclk_mmc2_fsys", + "sclk_mmc1_fsys", + "sclk_mmc0_fsys", + "sclk_usbhost30_fsys", + "sclk_usbdrd30_fsys"; + clocks = <&xxti>, + <&cmu_cpif CLK_SCLK_UFS_MPHY>, + <&cmu_top CLK_DIV_ACLK_FSYS_200>, + <&cmu_top CLK_SCLK_PCIE_100_FSYS>, + <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, + <&cmu_top CLK_SCLK_MMC2_FSYS>, + <&cmu_top CLK_SCLK_MMC1_FSYS>, + <&cmu_top CLK_SCLK_MMC0_FSYS>, + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_top CLK_SCLK_USBDRD30_FSYS>; + }; + + cmu_g2d: clock-controller@0x12460000 { + compatible = "samsung,exynos5433-cmu-g2d"; + reg = <0x12460000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_g2d_266", + "aclk_g2d_400"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_G2D_266>, + <&cmu_top CLK_ACLK_G2D_400>; + }; + + cmu_disp: clock-controller@0x13b90000 { + compatible = "samsung,exynos5433-cmu-disp"; + reg = <0x13b90000 0x0c04>; + #clock-cells = <1>; + + clock-names = "oscclk", + "sclk_dsim1_disp", + "sclk_dsim0_disp", + "sclk_dsd_disp", + "sclk_decon_tv_eclk_disp", + "sclk_decon_vclk_disp", + "sclk_decon_eclk_disp", + "sclk_decon_tv_vclk_disp", + "aclk_disp_333"; + clocks = <&xxti>, + <&cmu_mif CLK_SCLK_DSIM1_DISP>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_mif CLK_SCLK_DSD_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, + <&cmu_mif CLK_ACLK_DISP_333>; + }; + + cmu_aud: clock-controller@0x114c0000 { + compatible = "samsung,exynos5433-cmu-aud"; + reg = <0x114c0000 0x0b04>; + #clock-cells = <1>; + }; + + cmu_bus0: clock-controller@0x13600000 { + compatible = "samsung,exynos5433-cmu-bus0"; + reg = <0x13600000 0x0b04>; + #clock-cells = <1>; + + clock-names = "aclk_bus0_400"; + clocks = <&cmu_top CLK_ACLK_BUS0_400>; + }; + + cmu_bus1: clock-controller@0x14800000 { + compatible = "samsung,exynos5433-cmu-bus1"; + reg = <0x14800000 0x0b04>; + #clock-cells = <1>; + + clock-names = "aclk_bus1_400"; + clocks = <&cmu_top CLK_ACLK_BUS1_400>; + }; + + cmu_bus2: clock-controller@0x13400000 { + compatible = "samsung,exynos5433-cmu-bus2"; + reg = <0x13400000 0x0b04>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_bus2_400"; + clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; + }; + + cmu_g3d: clock-controller@0x14aa0000 { + compatible = "samsung,exynos5433-cmu-g3d"; + reg = <0x14aa0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_g3d_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; + }; + + cmu_gscl: clock-controller@0x13cf0000 { + compatible = "samsung,exynos5433-cmu-gscl"; + reg = <0x13cf0000 0x0b10>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_gscl_111", + "aclk_gscl_333"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_GSCL_111>, + <&cmu_top CLK_ACLK_GSCL_333>; + }; + +Example 3: UART controller node that consumes the clock generated by the clock + controller. + + serial_0: serial@14C10000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14C10000 0x100>; + interrupts = <0 421 0>; + clocks = <&cmu_peric CLK_PCLK_UART0>, + <&cmu_peric CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + status = "disabled"; + }; + +Example 4: SPI controller node that consumes the clock generated by the clock + controller. + + spi_0: spi@14d20000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d20000 0x100>; + interrupts = <0 432 0>; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI0>, + <&cmu_top CLK_SCLK_SPI0_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + };