From patchwork Mon Feb 2 13:10:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 5761971 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B2430BF440 for ; Mon, 2 Feb 2015 13:11:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2BEC1203A4 for ; Mon, 2 Feb 2015 13:11:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B1C57203A1 for ; Mon, 2 Feb 2015 13:11:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933280AbbBBNKv (ORCPT ); Mon, 2 Feb 2015 08:10:51 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:32658 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932372AbbBBNKs (ORCPT ); Mon, 2 Feb 2015 08:10:48 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NJ5002UNB9SH1B0@mailout4.samsung.com>; Mon, 02 Feb 2015 22:10:41 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.116]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id B6.0D.18484.0577FC45; Mon, 02 Feb 2015 22:10:40 +0900 (KST) X-AuditID: cbfee68f-f791c6d000004834-df-54cf7750c6c7 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 79.2B.09430.0577FC45; Mon, 02 Feb 2015 22:10:40 +0900 (KST) Received: from chan.10.32.193.11 ([10.252.81.195]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NJ500EHMB9R6E80@mmp1.samsung.com>; Mon, 02 Feb 2015 22:10:40 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com, mturquette@linaro.org Cc: kgene@kernel.org, pankaj.dubey@samsung.com, sangbae90.lee@samsung.com, inki.dae@samsung.com, chanho61.park@samsung.com, sw0312.kim@samsung.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/9] clk: samsung: exynos5433: Add clocks for CMU_ISP domain Date: Mon, 02 Feb 2015 22:10:33 +0900 Message-id: <1422882636-20464-7-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.5.5 In-reply-to: <1422882636-20464-1-git-send-email-cw00.choi@samsung.com> References: <1422882636-20464-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKLMWRmVeSWpSXmKPExsWyRsSkRDeg/HyIweVHJhaX92tbXP/ynNVi 0v0JLBb9j18zW1zeNYfNYsb5fUwWTydcZLNYtPULu8XhN+2sFsc/HWSxmDH5JZvFql1/GB14 PHbOusvusWlVJ5vHnWt72Dz6tqxi9Pi8SS6ANYrLJiU1J7MstUjfLoEro+/SHeaC3gmMFb0P 97M1MHZXdzFyckgImEgsPriTCcIWk7hwbz1bFyMXh5DAUkaJm5famWCKLm3axQKRWMQo8bxx JpTTxCRxau1ddpAqNgEtif0vbrCB2CICHhKnn90EK2IW+MAosX/iRCCHg0NYwF/ixyYukBoW AVWJ5nvPwTbwCrhK3Dp0HmqbgsSy5TNZQWxOATeJJVO3MILYQkA1Jy+2g50nIXCIXeLu48eM EIMEJL5NPgQ2X0JAVmLTAWaIOZISB1fcYJnAKLyAkWEVo2hqQXJBcVJ6kbFecWJucWleul5y fu4mRmBsnP73rH8H490D1ocYBTgYlXh4Ld6fCxFiTSwrrsw9xGgKtGEis5Rocj4wAvNK4g2N zYwsTE1MjY3MLc2UxHkXSv0MFhJITyxJzU5NLUgtii8qzUktPsTIxMEp1cAYdP7tn9JnBt6X q55GL/3Ms88i8fD5Sr6SP0mmxy5WyGrdOPBNVjbO2vrw6kvX7Nr3HVswaT7PDdY1WwU6+PU6 eGfe1WPhOCDavsfrWtCe0FUf1lu4Jr9dvnvp0X0pGW9OMHzi3n9Kbefz69fYOOwebjvQU2V/ 8dwZk6i0Ha05TKIznuytP/vqnhJLcUaioRZzUXEiABiy7BWIAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrPIsWRmVeSWpSXmKPExsVy+t9jAd2A8vMhBps+qVtc3q9tcf3Lc1aL SfcnsFj0P37NbHF51xw2ixnn9zFZPJ1wkc1i0dYv7BaH37SzWhz/dJDFYsbkl2wWq3b9YXTg 8dg56y67x6ZVnWwed67tYfPo27KK0ePzJrkA1qgGRpuM1MSU1CKF1Lzk/JTMvHRbJe/geOd4 UzMDQ11DSwtzJYW8xNxUWyUXnwBdt8wcoPuUFMoSc0qBQgGJxcVK+naYJoSGuOlawDRG6PqG BMH1GBmggYQ1jBl9l+4wF/ROYKzofbifrYGxu7qLkZNDQsBE4tKmXSwQtpjEhXvr2boYuTiE BBYxSjxvnMkC4TQxSZxae5cdpIpNQEti/4sbbCC2iICHxOlnN8GKmAU+MErsnzgRyOHgEBbw l/ixiQukhkVAVaL53nMmEJtXwFXi1qHzTBDbFCSWLZ/JCmJzCrhJLJm6hRHEFgKqOXmxnW0C I+8CRoZVjKKpBckFxUnpuUZ6xYm5xaV56XrJ+bmbGMGR90x6B+OqBotDjAIcjEo8vDcNzocI sSaWFVfmHmKU4GBWEuHVsAAK8aYkVlalFuXHF5XmpBYfYjQFumois5Rocj4wKeSVxBsam5gZ WRqZG1oYGZsrifMq2beFCAmkJ5akZqemFqQWwfQxcXBKNTAa7heZdOjzQunOvoYPz28Vh6bp fZd/J18Q8SA7d1X+97elCYLzt+5lmHtyon3YhW6xPwVvvFaffLAjdS3zQ+Yc1yI28Tkfm36d eO36d3/LgokyZxqWLu9i23TQR/XUYrs41zJpm//tK9YmCE05u13E1nxSuHZE3uRJzFHll1xX Gvcfbjnp9vCuEktxRqKhFnNRcSIAUgKTtdICAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the mux/divider/gate clocks for CMU_ISP domain which generates the clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Acked-by: Inki Dae --- .../devicetree/bindings/clock/exynos5433-clock.txt | 15 ++ drivers/clk/samsung/clk-exynos5433.c | 267 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 89 ++++++- 3 files changed, 370 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt index 2f4393d..9f16264 100644 --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt @@ -43,6 +43,8 @@ Required Properties: which generates clocks for MFC(Multi-Format Codec) IP. - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC which generates clocks for HEVC(High Efficiency Video Codec) decoder IP. + - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP + which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. - reg: physical base address of the controller and length of memory mapped region. @@ -282,6 +284,19 @@ Example 2: Examples of clock controller nodes are listed below. clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; }; + cmu_isp: clock-controller@146d0000 { + compatible = "samsung,exynos5433-cmu-isp"; + reg = <0x146d0000 0x0b0c>; + #clock-cells = <1>; + + clock-names = "oscclk", + "aclk_isp_dis_400", + "aclk_isp_400"; + clocks = <&xxti>, + <&cmu_top CLK_ACLK_ISP_DIS_400>, + <&cmu_top CLK_ACLK_ISP_400>; + }; + Example 3: UART controller node that consumes the clock generated by the clock controller. diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 08780c0..a7ec551 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -404,6 +404,12 @@ static struct samsung_mux_clock top_mux_clks[] __initdata = { }; static struct samsung_div_clock top_div_clks[] __initdata = { + /* DIV_TOP0 */ + DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400", + "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4), + DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400", + "mout_aclk_isp_400", DIV_TOP0, 0, 4), + /* DIV_TOP1 */ DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333", DIV_TOP1, 28, 3), @@ -560,6 +566,12 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = { GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333", ENABLE_ACLK_TOP, 14, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400", + ENABLE_ACLK_TOP, 7, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400", + ENABLE_ACLK_TOP, 6, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400", ENABLE_ACLK_TOP, 5, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), @@ -4218,3 +4230,258 @@ static void __init exynos5433_cmu_hevc_init(struct device_node *np) } CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc", exynos5433_cmu_hevc_init); + +/* + * Register offset definitions for CMU_ISP + */ +#define MUX_SEL_ISP 0x0200 +#define MUX_ENABLE_ISP 0x0300 +#define MUX_STAT_ISP 0x0400 +#define DIV_ISP 0x0600 +#define DIV_STAT_ISP 0x0700 +#define ENABLE_ACLK_ISP0 0x0800 +#define ENABLE_ACLK_ISP1 0x0804 +#define ENABLE_ACLK_ISP2 0x0808 +#define ENABLE_PCLK_ISP 0x0900 +#define ENABLE_SCLK_ISP 0x0a00 +#define ENABLE_IP_ISP0 0x0b00 +#define ENABLE_IP_ISP1 0x0b04 +#define ENABLE_IP_ISP2 0x0b08 +#define ENABLE_IP_ISP3 0x0b0c + +static unsigned long isp_clk_regs[] __initdata = { + MUX_SEL_ISP, + MUX_ENABLE_ISP, + MUX_STAT_ISP, + DIV_ISP, + DIV_STAT_ISP, + ENABLE_ACLK_ISP0, + ENABLE_ACLK_ISP1, + ENABLE_ACLK_ISP2, + ENABLE_PCLK_ISP, + ENABLE_SCLK_ISP, + ENABLE_IP_ISP0, + ENABLE_IP_ISP1, + ENABLE_IP_ISP2, + ENABLE_IP_ISP3, +}; + +PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", }; +PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", }; + +static struct samsung_mux_clock isp_mux_clks[] __initdata = { + /* MUX_SEL_ISP */ + MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user", + mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0), + MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user", + mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0), +}; + +static struct samsung_div_clock isp_div_clks[] __initdata = { + /* DIV_ISP */ + DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis", + "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3), + DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user", + DIV_ISP, 8, 3), + DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200", + "mout_aclk_isp_400_user", DIV_ISP, 4, 3), + DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200", + "mout_aclk_isp_400_user", DIV_ISP, 0, 3), +}; + +static struct samsung_gate_clock isp_gate_clks[] __initdata = { + /* ENABLE_ACLK_ISP0 */ + GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP0, 5, 0, 0), + GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP0, 4, 0, 0), + GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user", + ENABLE_ACLK_ISP0, 3, 0, 0), + GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP0, 2, 0, 0), + GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP0, 1, 0, 0), + GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP0, 0, 0, 0), + + /* ENABLE_ACLK_ISP1 */ + GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp", + "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, + 17, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc", + "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, + 16, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc", + "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, + 15, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p", + "div_pclk_isp", ENABLE_ACLK_ISP1, + 14, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p", + "div_pclk_isp", ENABLE_ACLK_ISP1, + 13, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1", + "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, + 12, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0", + "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, + 11, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1", + "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, + 10, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0", + "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, + 9, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p", + "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, + 8, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p", + "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, + 7, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp", + ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp", + ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p", + "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, + 4, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p", + "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, + 3, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), + + /* ENABLE_ACLK_ISP2 */ + GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp", + "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, + 13, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc", + "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, + 9, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp", + "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, + 6, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc", + "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, + 2, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user", + ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0), + + /* ENABLE_PCLK_ISP */ + GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200", + ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200", + ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200", + ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200", + ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200", + ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200", + ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200", + ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp", + ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp", + ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp", + ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp", + ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp", + ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp", + ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp", + ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp", + ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp", + ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp", + ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp", + ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local", + "div_aclk_isp_c_200", ENABLE_PCLK_ISP, + 7, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200", + ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200", + ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis", + ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200", + ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200", + ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200", + ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200", + ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0), + + /* ENABLE_SCLK_ISP */ + GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis", + "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, + 5, CLK_IGNORE_UNUSED, 0), + GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis", + "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, + 4, CLK_IGNORE_UNUSED, 0), + GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp", + "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, + 3, CLK_IGNORE_UNUSED, 0), + GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd", + "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, + 2, CLK_IGNORE_UNUSED, 0), + GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc", + "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, + 1, CLK_IGNORE_UNUSED, 0), + GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc", + "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, + 0, CLK_IGNORE_UNUSED, 0), +}; + +static struct samsung_cmu_info isp_cmu_info __initdata = { + .mux_clks = isp_mux_clks, + .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), + .div_clks = isp_div_clks, + .nr_div_clks = ARRAY_SIZE(isp_div_clks), + .gate_clks = isp_gate_clks, + .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), + .nr_clk_ids = ISP_NR_CLK, + .clk_regs = isp_clk_regs, + .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), +}; + +static void __init exynos5433_cmu_isp_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &isp_cmu_info); +} +CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp", + exynos5433_cmu_isp_init); diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 2b3ac5a..a38f420 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -116,6 +116,8 @@ #define CLK_DIV_SCLK_USBDRD30 143 #define CLK_DIV_SCLK_JPEG 144 #define CLK_DIV_ACLK_MSCL_400 145 +#define CLK_DIV_ACLK_ISP_DIS_400 146 +#define CLK_DIV_ACLK_ISP_400 147 #define CLK_ACLK_PERIC_66 200 #define CLK_ACLK_PERIS_66 201 @@ -155,8 +157,10 @@ #define CLK_ACLK_MSCL_400 235 #define CLK_ACLK_MFC_400 236 #define CLK_ACLK_HEVC_400 237 +#define CLK_ACLK_ISP_DIS_400 238 +#define CLK_ACLK_ISP_400 239 -#define TOP_NR_CLK 238 +#define TOP_NR_CLK 240 /* CMU_CPIF */ #define CLK_FOUT_MPHY_PLL 1 @@ -1026,4 +1030,87 @@ #define HEVC_NR_CLK 19 +/* CMU_ISP */ +#define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 +#define CLK_MOUT_ACLK_ISP_400_USER 2 + +#define CLK_DIV_PCLK_ISP_DIS 3 +#define CLK_DIV_PCLK_ISP 4 +#define CLK_DIV_ACLK_ISP_D_200 5 +#define CLK_DIV_ACLK_ISP_C_200 6 + +#define CLK_ACLK_ISP_D_GLUE 7 +#define CLK_ACLK_SCALERP 8 +#define CLK_ACLK_3DNR 9 +#define CLK_ACLK_DIS 10 +#define CLK_ACLK_SCALERC 11 +#define CLK_ACLK_DRC 12 +#define CLK_ACLK_ISP 13 +#define CLK_ACLK_AXIUS_SCALERP 14 +#define CLK_ACLK_AXIUS_SCALERC 15 +#define CLK_ACLK_AXIUS_DRC 16 +#define CLK_ACLK_ASYNCAHBM_ISP2P 17 +#define CLK_ACLK_ASYNCAHBM_ISP1P 18 +#define CLK_ACLK_ASYNCAXIS_DIS1 19 +#define CLK_ACLK_ASYNCAXIS_DIS0 20 +#define CLK_ACLK_ASYNCAXIM_DIS1 21 +#define CLK_ACLK_ASYNCAXIM_DIS0 22 +#define CLK_ACLK_ASYNCAXIM_ISP2P 23 +#define CLK_ACLK_ASYNCAXIM_ISP1P 24 +#define CLK_ACLK_AHB2APB_ISP2P 25 +#define CLK_ACLK_AHB2APB_ISP1P 26 +#define CLK_ACLK_AXI2APB_ISP2P 27 +#define CLK_ACLK_AXI2APB_ISP1P 28 +#define CLK_ACLK_XIU_ISPEX1 29 +#define CLK_ACLK_XIU_ISPEX0 30 +#define CLK_ACLK_ISPND_400 31 +#define CLK_ACLK_SMMU_SCALERP 32 +#define CLK_ACLK_SMMU_3DNR 33 +#define CLK_ACLK_SMMU_DIS1 34 +#define CLK_ACLK_SMMU_DIS0 35 +#define CLK_ACLK_SMMU_SCALERC 36 +#define CLK_ACLK_SMMU_DRC 37 +#define CLK_ACLK_SMMU_ISP 38 +#define CLK_ACLK_BTS_SCALERP 39 +#define CLK_ACLK_BTS_3DR 40 +#define CLK_ACLK_BTS_DIS1 41 +#define CLK_ACLK_BTS_DIS0 42 +#define CLK_ACLK_BTS_SCALERC 43 +#define CLK_ACLK_BTS_DRC 44 +#define CLK_ACLK_BTS_ISP 45 +#define CLK_PCLK_SMMU_SCALERP 46 +#define CLK_PCLK_SMMU_3DNR 47 +#define CLK_PCLK_SMMU_DIS1 48 +#define CLK_PCLK_SMMU_DIS0 49 +#define CLK_PCLK_SMMU_SCALERC 50 +#define CLK_PCLK_SMMU_DRC 51 +#define CLK_PCLK_SMMU_ISP 52 +#define CLK_PCLK_BTS_SCALERP 53 +#define CLK_PCLK_BTS_3DNR 54 +#define CLK_PCLK_BTS_DIS1 55 +#define CLK_PCLK_BTS_DIS0 56 +#define CLK_PCLK_BTS_SCALERC 57 +#define CLK_PCLK_BTS_DRC 58 +#define CLK_PCLK_BTS_ISP 59 +#define CLK_PCLK_ASYNCAXI_DIS1 60 +#define CLK_PCLK_ASYNCAXI_DIS0 61 +#define CLK_PCLK_PMU_ISP 62 +#define CLK_PCLK_SYSREG_ISP 63 +#define CLK_PCLK_CMU_ISP_LOCAL 64 +#define CLK_PCLK_SCALERP 65 +#define CLK_PCLK_3DNR 66 +#define CLK_PCLK_DIS_CORE 67 +#define CLK_PCLK_DIS 68 +#define CLK_PCLK_SCALERC 69 +#define CLK_PCLK_DRC 70 +#define CLK_PCLK_ISP 71 +#define CLK_SCLK_PIXELASYNCS_DIS 72 +#define CLK_SCLK_PIXELASYNCM_DIS 73 +#define CLK_SCLK_PIXELASYNCS_SCALERP 74 +#define CLK_SCLK_PIXELASYNCM_ISPD 75 +#define CLK_SCLK_PIXELASYNCS_ISPC 76 +#define CLK_SCLK_PIXELASYNCM_ISPC 77 + +#define ISP_NR_CLK 78 + #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */