From patchwork Mon Feb 2 14:23:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 5762451 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E26CB9F380 for ; Mon, 2 Feb 2015 14:24:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BD35F204E1 for ; Mon, 2 Feb 2015 14:24:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8E5C2204E0 for ; Mon, 2 Feb 2015 14:24:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754112AbbBBOYR (ORCPT ); Mon, 2 Feb 2015 09:24:17 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:62356 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752428AbbBBOYK (ORCPT ); Mon, 2 Feb 2015 09:24:10 -0500 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NJ5008EFEO89H30@mailout1.samsung.com>; Mon, 02 Feb 2015 23:24:08 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.114]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 7E.A1.17016.8888FC45; Mon, 02 Feb 2015 23:24:08 +0900 (KST) X-AuditID: cbfee68d-f79296d000004278-3d-54cf8888c40c Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 63.86.09430.8888FC45; Mon, 02 Feb 2015 23:24:08 +0900 (KST) Received: from chan.10.32.193.11 ([10.252.81.195]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NJ50082HEO73840@mmp2.samsung.com>; Mon, 02 Feb 2015 23:24:08 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com, mturquette@linaro.org Cc: kgene@kernel.org, pankaj.dubey@samsung.com, sangbae90.lee@samsung.com, inki.dae@samsung.com, chanho61.park@samsung.com, sw0312.kim@samsung.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Inha Song Subject: [PATCH v5 04/13] clk: samsung: exynos5433: Add clocks for CMU_PERIC domain Date: Mon, 02 Feb 2015 23:23:58 +0900 Message-id: <1422887047-30911-5-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.5.5 In-reply-to: <1422887047-30911-1-git-send-email-cw00.choi@samsung.com> References: <1422887047-30911-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrLLMWRmVeSWpSXmKPExsWyRsSkSLej43yIwdYtGhaX92tbXP/ynNVi /pFzrBa7/t5ntJh0fwKLRf/j18wWl3fNYbOYcX4fk8XTCRfZLBZt/cJucfhNO6vF8U8HWSxm TH7JZrFq1x9GBz6PnbPusntsWtXJ5nHn2h42j74tqxg9Pm+SC2CN4rJJSc3JLEst0rdL4Mo4 1pdd8NO94mh7fANjq10XIyeHhICJxNxFB5ggbDGJC/fWs3UxcnEICSxllHj+8CETTNHOWweZ IRLTGSWe/d3KAuE0MUnsOveJGaSKTUBLYv+LG2wgtoiAh8TpZzfBipgFNjFJPH3yFSwhLBAq cWjWRrAGFgFVidNv17CA2LwCrhJbj31hh1inILFs+UxWEJtTwE3izsHXYGcIAdVMnrudFWSo hMApdomlM68yQQwSkPg2+RDQIA6ghKzEpgPMEHMkJQ6uuMEygVF4ASPDKkbR1ILkguKk9CJD veLE3OLSvHS95PzcTYzAWDn971nvDsbbB6wPMQpwMCrx8Fq8PxcixJpYVlyZe4jRFGjDRGYp 0eR8YETmlcQbGpsZWZiamBobmVuaKYnzKkr9DBYSSE8sSc1OTS1ILYovKs1JLT7EyMTBKdXA OKW3ZsKxvS81jVefTVI8f+9u57nHZ0/zM1XvObmAa4vtjQxPpnfur89MvLx/l1V48fq6V6eS P8jEpH38tqqRSV3i4IaZwczJPtvCzP+fqKh/9DB/bnvgv6QJW3Yl7rXRN0yf8sTou2md+tlv R28ulkv1/PA8+dmS1X0lDknGrYwr+5T+f9gZrarEUpyRaKjFXFScCACpndyekAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOIsWRmVeSWpSXmKPExsVy+t9jQd2OjvMhBs/Wy1pc3q9tcf3Lc1aL +UfOsVrs+nuf0WLS/QksFv2PXzNbXN41h81ixvl9TBZPJ1xks1i09Qu7xeE37awWxz8dZLGY Mfklm8WqXX8YHfg8ds66y+6xaVUnm8eda3vYPPq2rGL0+LxJLoA1qoHRJiM1MSW1SCE1Lzk/ JTMv3VbJOzjeOd7UzMBQ19DSwlxJIS8xN9VWycUnQNctMwfoUiWFssScUqBQQGJxsZK+HaYJ oSFuuhYwjRG6viFBcD1GBmggYQ1jxrG+7IKf7hVH2+MbGFvtuhg5OSQETCR23jrIDGGLSVy4 t56ti5GLQ0hgOqPEs79bWSCcJiaJXec+gVWxCWhJ7H9xgw3EFhHwkDj97CZYEbPAJiaJp0++ giWEBUIlDs3aCNbAIqAqcfrtGhYQm1fAVWLrsS/sEOsUJJYtn8kKYnMKuEncOfiaCcQWAqqZ PHc76wRG3gWMDKsYRVMLkguKk9JzjfSKE3OLS/PS9ZLzczcxgiPxmfQOxlUNFocYBTgYlXh4 bxqcDxFiTSwrrsw9xCjBwawkwqthARTiTUmsrEotyo8vKs1JLT7EaAp01URmKdHkfGCSyCuJ NzQ2MTOyNDI3tDAyNlcS51WybwsREkhPLEnNTk0tSC2C6WPi4JRqYAzVYte5duSGn+f539ZM l7xXKv0usc6S+cCmM3F2tq6krtqCTw/3W11n6Lh/VW1/snxoXVrC9aqnht3KOhc8DR/tvdok uaBhL+/fF4yOU3+yWlm075u+wk+qYefWc/PVC0Kv3tj5fI/knR0LDljedPvu9zLJ9Snnbo22 7t65KT0ym1+lH/GNkVNiKc5INNRiLipOBADHExo92gIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds missing divider/gate clocks of CMU_PERIC domain which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use external input clock which has 'ioclk_*' prefix. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi [ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on.] Signed-off-by: Inha Song Acked-by: Inki Dae --- drivers/clk/samsung/clk-exynos5433.c | 83 +++++++++++++++++++++++++++++++++- include/dt-bindings/clock/exynos5433.h | 34 +++++++++++++- 2 files changed, 114 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 31ec700..9c2cb19 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -251,6 +251,14 @@ static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = { FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000), /* Xi2s1SDI input clock for SPDIF */ FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000), + /* XspiCLK[4:0] input clock for SPI */ + FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000), + FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000), + FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000), + FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000), + FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000), + /* Xi2s1SCLK input clock for I2S1_BCLK */ + FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000), }; static struct samsung_mux_clock top_mux_clks[] __initdata = { @@ -756,6 +764,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", * Register offset definitions for CMU_PERIC */ #define DIV_PERIC 0x0600 +#define DIV_STAT_PERIC 0x0700 #define ENABLE_ACLK_PERIC 0x0800 #define ENABLE_PCLK_PERIC0 0x0900 #define ENABLE_PCLK_PERIC1 0x0904 @@ -766,6 +775,7 @@ CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", static unsigned long peric_clk_regs[] __initdata = { DIV_PERIC, + DIV_STAT_PERIC, ENABLE_ACLK_PERIC, ENABLE_PCLK_PERIC0, ENABLE_PCLK_PERIC1, @@ -775,14 +785,57 @@ static unsigned long peric_clk_regs[] __initdata = { ENABLE_IP_PERIC2, }; +static struct samsung_div_clock peric_div_clks[] __initdata = { + /* DIV_PERIC */ + DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), + DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), +}; + static struct samsung_gate_clock peric_gate_clks[] __initdata = { + /* ENABLE_ACLK_PERIC */ + GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", + ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66", + ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66", + ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66", + ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0), + /* ENABLE_PCLK_PERIC0 */ + GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0, + 31, CLK_SET_RATE_PARENT, 0), + GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66", + ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66", + ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0, + 28, CLK_SET_RATE_PARENT, 0), + GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0, + 26, CLK_SET_RATE_PARENT, 0), + GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0, + 25, CLK_SET_RATE_PARENT, 0), + GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0, + 24, CLK_SET_RATE_PARENT, 0), GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 23, CLK_SET_RATE_PARENT, 0), GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 22, CLK_SET_RATE_PARENT, 0), GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0, + 20, CLK_SET_RATE_PARENT, 0), + GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66", + ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66", + ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66", + ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66", + ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0), + GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66", + ENABLE_PCLK_PERIC0, 15, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 14, CLK_SET_RATE_PARENT, 0), GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0, @@ -837,15 +890,39 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), /* ENABLE_SCLK_PERIC */ + GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in", + ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in", + ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC, 19, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), - + GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC, + 17, 0, 0), + GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC, + 16, 0, 0), + GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0), + GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in", + ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", + ENABLE_SCLK_PERIC, 12, + CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", + ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", + "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric", + ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric", + ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric", + ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, 5, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, - 4, CLK_SET_RATE_PARENT, 0), + 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", @@ -857,6 +934,8 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { }; static struct samsung_cmu_info peric_cmu_info __initdata = { + .div_clks = peric_div_clks, + .nr_div_clks = ARRAY_SIZE(peric_div_clks), .gate_clks = peric_gate_clks, .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), .nr_clk_ids = PERIC_NR_CLK, diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 6025006..62d3ec7 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -181,8 +181,40 @@ #define CLK_SCLK_UART2 34 #define CLK_SCLK_UART1 35 #define CLK_SCLK_UART0 36 +#define CLK_ACLK_AHB2APB_PERIC2P 37 +#define CLK_ACLK_AHB2APB_PERIC1P 38 +#define CLK_ACLK_AHB2APB_PERIC0P 39 +#define CLK_ACLK_PERICNP_66 40 +#define CLK_PCLK_SCI 41 +#define CLK_PCLK_GPIO_FINGER 42 +#define CLK_PCLK_GPIO_ESE 43 +#define CLK_PCLK_PWM 44 +#define CLK_PCLK_SPDIF 45 +#define CLK_PCLK_PCM1 46 +#define CLK_PCLK_I2S1 47 +#define CLK_PCLK_ADCIF 48 +#define CLK_PCLK_GPIO_TOUCH 49 +#define CLK_PCLK_GPIO_NFC 50 +#define CLK_PCLK_GPIO_PERIC 51 +#define CLK_PCLK_PMU_PERIC 52 +#define CLK_PCLK_SYSREG_PERIC 53 +#define CLK_SCLK_IOCLK_SPI4 54 +#define CLK_SCLK_IOCLK_SPI3 55 +#define CLK_SCLK_SCI 56 +#define CLK_SCLK_SC_IN 57 +#define CLK_SCLK_PWM 58 +#define CLK_SCLK_IOCLK_SPI2 59 +#define CLK_SCLK_IOCLK_SPI1 60 +#define CLK_SCLK_IOCLK_SPI0 61 +#define CLK_SCLK_IOCLK_I2S1_BCLK 62 +#define CLK_SCLK_SPDIF 63 +#define CLK_SCLK_PCM1 64 +#define CLK_SCLK_I2S1 65 -#define PERIC_NR_CLK 37 +#define CLK_DIV_SCLK_SCI 70 +#define CLK_DIV_SCLK_SC_IN 71 + +#define PERIC_NR_CLK 72 /* CMU_PERIS */ #define CLK_PCLK_HPM_APBIF 1