From patchwork Tue Feb 3 00:13:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 5765641 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AA6D69F302 for ; Tue, 3 Feb 2015 00:16:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 910EA209FE for ; Tue, 3 Feb 2015 00:16:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4B20F209EC for ; Tue, 3 Feb 2015 00:16:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965371AbbBCAQq (ORCPT ); Mon, 2 Feb 2015 19:16:46 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:40986 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965347AbbBCAOH (ORCPT ); Mon, 2 Feb 2015 19:14:07 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NJ600COF5ZEWL10@mailout1.samsung.com>; Tue, 03 Feb 2015 09:14:02 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.113]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 15.EB.18484.AC210D45; Tue, 03 Feb 2015 09:14:02 +0900 (KST) X-AuditID: cbfee68f-f791c6d000004834-93-54d012ca8902 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 78.6C.09430.AC210D45; Tue, 03 Feb 2015 09:14:02 +0900 (KST) Received: from chan.10.32.193.11 ([10.252.81.195]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NJ6000EG5ZD2HJ0@mmp2.samsung.com>; Tue, 03 Feb 2015 09:14:01 +0900 (KST) From: Chanwoo Choi To: s.nawrocki@samsung.com, tomasz.figa@gmail.com, mturquette@linaro.org Cc: kgene@kernel.org, pankaj.dubey@samsung.com, inki.dae@samsung.com, chanho61.park@samsung.com, sw0312.kim@samsung.com, cw00.choi@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 4/9] clk: samsung: exynos5433: Add clocks for CMU_MFC domain Date: Tue, 03 Feb 2015 09:13:52 +0900 Message-id: <1422922437-7414-5-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.5.5 In-reply-to: <1422922437-7414-1-git-send-email-cw00.choi@samsung.com> References: <1422922437-7414-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrCLMWRmVeSWpSXmKPExsWyRsSkUPeU0IUQg6lTJSwu79e2uP7lOavF /CPnWC0m3Z/AYtH/+DWzxeVdc9gsZpzfx2TxdMJFNotFW7+wWxx+085qMWPySzaLVbv+MDrw eOycdZfdY9OqTjaPO9f2sHn0bVnF6PF5k1wAaxSXTUpqTmZZapG+XQJXxqaTS5gLdjlUnHlz hrWBcY5ZFyMnh4SAicS/TwfZIWwxiQv31rN1MXJxCAksZZQ4fvk7E0xR+59PzBCJ6YwSx37M YwFJCAk0MUn0TTIBsdkEtCT2v7jBBmKLCHhInH52kwWkgVngI6PE0gMrwVYIC/hLPOz6ygpi swioSkxfuZ4RxOYVcJGYtX8jG8Q2BYlly2eC1XAKuEosft3PDrHMRaKr8wUjyFAJgUPsElP+ T2SHGCQg8W3yIaBtHEAJWYlNB5gh5khKHFxxg2UCo/ACRoZVjKKpBckFxUnpRcZ6xYm5xaV5 6XrJ+bmbGIGRcfrfs/4djHcPWB9iFOBgVOLhtXh/LkSINbGsuDL3EKMp0IaJzFKiyfnA+Msr iTc0NjOyMDUxNTYytzRTEuddKPUzWEggPbEkNTs1tSC1KL6oNCe1+BAjEwenVAOj0JG5y5dY R5c6v3tlFbra3700rGqV/ZR5dSn5mQ3vrqgwOB89ckCtUd7nWtn0GzrWEjO28wpKiV/8s++A 8JZ1L92zC3lVlngePHcqd+v7K1Htb344FrgYpD25H8aqUpRcc7L/etvXky3/DBX+zrWxFc7g lrvKr3NZ7/nv7+7BOV/zWw41zZysxFKckWioxVxUnAgAP82saYcCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHIsWRmVeSWpSXmKPExsVy+t9jQd1TQhdCDM7d57O4vF/b4vqX56wW 84+cY7WYdH8Ci0X/49fMFpd3zWGzmHF+H5PF0wkX2SwWbf3CbnH4TTurxYzJL9ksVu36w+jA 47Fz1l12j02rOtk87lzbw+bRt2UVo8fnTXIBrFENjDYZqYkpqUUKqXnJ+SmZeem2St7B8c7x pmYGhrqGlhbmSgp5ibmptkouPgG6bpk5QPcpKZQl5pQChQISi4uV9O0wTQgNcdO1gGmM0PUN CYLrMTJAAwlrGDM2nVzCXLDLoeLMmzOsDYxzzLoYOTkkBEwk2v98YoawxSQu3FvP1sXIxSEk MJ1R4tiPeSwgCSGBJiaJvkkmIDabgJbE/hc32EBsEQEPidPPbrKANDALfGSUWHpgJTtIQljA X+Jh11dWEJtFQFVi+sr1jCA2r4CLxKz9G9kgtilILFs+E6yGU8BVYvHrfnaIZS4SXZ0vGCcw 8i5gZFjFKJpakFxQnJSea6RXnJhbXJqXrpecn7uJERx3z6R3MK5qsDjEKMDBqMTDe9PgfIgQ a2JZcWXuIUYJDmYlEV6/M0Ah3pTEyqrUovz4otKc1OJDjKZAV01klhJNzgemhLySeENjEzMj SyNzQwsjY3MlcV4l+7YQIYH0xJLU7NTUgtQimD4mDk6pBsbVE7riNn5607R7iU7UTufKCa7X lb8pr3mw+d46kSOTryyq87S/+6vgY/W/ateFEfsyJ093kdk63WRd7Iq3kie2+vLvcdxjzmjp XzgvtJS76uGR6899HN6oLnt23ElG79updSfNW9/n1Gxc0DP7qZJxpqdtzYLX/Zc9mlT0SyNV +b0XLvobk5arxFKckWioxVxUnAgA3BMdAtECAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the mux/divider/gate clocks for CMU_MFC domain which generates the clocks for MFC(Multi-Format Codec) IP. Cc: Sylwester Nawrocki Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Acked-by: Inki Dae --- .../devicetree/bindings/clock/exynos5433-clock.txt | 15 +++ drivers/clk/samsung/clk-exynos5433.c | 113 +++++++++++++++++++++ include/dt-bindings/clock/exynos5433.h | 27 ++++- 3 files changed, 154 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt index ecb9534..0f35167 100644 --- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt @@ -39,6 +39,8 @@ Required Properties: L2 cache controller. - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs. + - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC + which generates clocks for MFC(Multi-Format Codec) IP. - reg: physical base address of the controller and length of memory mapped region. @@ -125,6 +127,10 @@ Required Properties: - sclk_jpeg_mscl - aclk_mscl_400 + Input clocks for mfc clock controller: + - oscclk + - aclk_mfc_400 + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -340,6 +346,15 @@ Example 2: Examples of clock controller nodes are listed below. <&cmu_top CLK_ACLK_MSCL_400>; }; + cmu_mfc: clock-controller@15280000 { + compatible = "samsung,exynos5433-cmu-mfc"; + reg = <0x15280000 0x0b08>; + #clock-cells = <1>; + + clock-names = "oscclk", "aclk_mfc_400"; + clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; + }; + Example 3: UART controller node that consumes the clock generated by the clock controller. diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index a5238cd..2033b07 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -560,6 +560,9 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = { GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333", ENABLE_ACLK_TOP, 14, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400", + ENABLE_ACLK_TOP, 3, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266", ENABLE_ACLK_TOP, 2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), @@ -3990,3 +3993,113 @@ static void __init exynos5433_cmu_mscl_init(struct device_node *np) } CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl", exynos5433_cmu_mscl_init); + +/* + * Register offset definitions for CMU_MFC + */ +#define MUX_SEL_MFC 0x0200 +#define MUX_ENABLE_MFC 0x0300 +#define MUX_STAT_MFC 0x0400 +#define DIV_MFC 0x0600 +#define DIV_STAT_MFC 0x0700 +#define ENABLE_ACLK_MFC 0x0800 +#define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804 +#define ENABLE_PCLK_MFC 0x0900 +#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904 +#define ENABLE_IP_MFC0 0x0b00 +#define ENABLE_IP_MFC1 0x0b04 +#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08 + +static unsigned long mfc_clk_regs[] __initdata = { + MUX_SEL_MFC, + MUX_ENABLE_MFC, + MUX_STAT_MFC, + DIV_MFC, + DIV_STAT_MFC, + ENABLE_ACLK_MFC, + ENABLE_ACLK_MFC_SECURE_SMMU_MFC, + ENABLE_PCLK_MFC, + ENABLE_PCLK_MFC_SECURE_SMMU_MFC, + ENABLE_IP_MFC0, + ENABLE_IP_MFC1, + ENABLE_IP_MFC_SECURE_SMMU_MFC, +}; + +PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", }; + +static struct samsung_mux_clock mfc_mux_clks[] __initdata = { + /* MUX_SEL_MFC */ + MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user", + mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0), +}; + +static struct samsung_div_clock mfc_div_clks[] __initdata = { + /* DIV_MFC */ + DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user", + DIV_MFC, 0, 2), +}; + +static struct samsung_gate_clock mfc_gate_clks[] __initdata = { + /* ENABLE_ACLK_MFC */ + GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user", + ENABLE_ACLK_MFC, 6, 0, 0), + GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user", + ENABLE_ACLK_MFC, 5, 0, 0), + GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc", + ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user", + ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc", + ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user", + ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user", + ENABLE_ACLK_MFC, 0, 0, 0), + + /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */ + GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user", + ENABLE_ACLK_MFC_SECURE_SMMU_MFC, + 1, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user", + ENABLE_ACLK_MFC_SECURE_SMMU_MFC, + 0, CLK_IGNORE_UNUSED, 0), + + /* ENABLE_PCLK_MFC */ + GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc", + ENABLE_PCLK_MFC, 4, 0, 0), + GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc", + ENABLE_PCLK_MFC, 3, 0, 0), + GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc", + ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc", + ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc", + ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0), + + /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */ + GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc", + ENABLE_PCLK_MFC_SECURE_SMMU_MFC, + 1, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc", + ENABLE_PCLK_MFC_SECURE_SMMU_MFC, + 0, CLK_IGNORE_UNUSED, 0), +}; + +static struct samsung_cmu_info mfc_cmu_info __initdata = { + .mux_clks = mfc_mux_clks, + .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), + .div_clks = mfc_div_clks, + .nr_div_clks = ARRAY_SIZE(mfc_div_clks), + .gate_clks = mfc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), + .nr_clk_ids = MFC_NR_CLK, + .clk_regs = mfc_clk_regs, + .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), +}; + +static void __init exynos5433_cmu_mfc_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &mfc_cmu_info); +} +CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc", + exynos5433_cmu_mfc_init); diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 757c419..dfeb9d6 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -153,8 +153,9 @@ #define CLK_ACLK_GSCL_333 233 #define CLK_SCLK_JPEG_MSCL 234 #define CLK_ACLK_MSCL_400 235 +#define CLK_ACLK_MFC_400 236 -#define TOP_NR_CLK 236 +#define TOP_NR_CLK 237 /* CMU_CPIF */ #define CLK_FOUT_MPHY_PLL 1 @@ -976,4 +977,28 @@ #define MSCL_NR_CLK 30 +/* CMU_MFC */ +#define CLK_MOUT_ACLK_MFC_400_USER 1 + +#define CLK_DIV_PCLK_MFC 2 + +#define CLK_ACLK_BTS_MFC_1 3 +#define CLK_ACLK_BTS_MFC_0 4 +#define CLK_ACLK_AHB2APB_MFCP 5 +#define CLK_ACLK_XIU_MFCX 6 +#define CLK_ACLK_MFCNP_100 7 +#define CLK_ACLK_MFCND_400 8 +#define CLK_ACLK_MFC 9 +#define CLK_ACLK_SMMU_MFC_1 10 +#define CLK_ACLK_SMMU_MFC_0 11 +#define CLK_PCLK_BTS_MFC_1 12 +#define CLK_PCLK_BTS_MFC_0 13 +#define CLK_PCLK_PMU_MFC 14 +#define CLK_PCLK_SYSREG_MFC 15 +#define CLK_PCLK_MFC 16 +#define CLK_PCLK_SMMU_MFC_1 17 +#define CLK_PCLK_SMMU_MFC_0 18 + +#define MFC_NR_CLK 19 + #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */