From patchwork Thu Feb 5 12:35:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 5784331 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9E75BBF440 for ; Thu, 5 Feb 2015 12:37:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BF326201E4 for ; Thu, 5 Feb 2015 12:37:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DB8D820268 for ; Thu, 5 Feb 2015 12:37:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757241AbbBEMgq (ORCPT ); Thu, 5 Feb 2015 07:36:46 -0500 Received: from mailout3.w1.samsung.com ([210.118.77.13]:9051 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757366AbbBEMgQ (ORCPT ); Thu, 5 Feb 2015 07:36:16 -0500 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NJA000CDTV55J60@mailout3.w1.samsung.com>; Thu, 05 Feb 2015 12:40:17 +0000 (GMT) X-AuditID: cbfec7f5-b7fc86d0000066b7-d3-54d3632b657a Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 37.58.26295.B2363D45; Thu, 05 Feb 2015 12:33:47 +0000 (GMT) Received: from AMDC1061.digital.local ([106.116.147.88]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0NJA00AIBTO3X990@eusync2.samsung.com>; Thu, 05 Feb 2015 12:36:13 +0000 (GMT) From: Andrzej Hajda To: linux-samsung-soc@vger.kernel.org Cc: Andrzej Hajda , Marek Szyprowski , Kyungmin Park , Kukjin Kim , javier.martinez@collabora.co.uk, Liquid.Acid@gmx.net, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [RFC PATCH 2/3] arm/exynos/pm_domains: add support for async-bridge clocks Date: Thu, 05 Feb 2015 13:35:38 +0100 Message-id: <1423139739-19881-3-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1423139739-19881-1-git-send-email-a.hajda@samsung.com> References: <1423139739-19881-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgluLIzCtJLcpLzFFi42I5/e/4FV3t5MshBu/2ClncWneO1WL+ESBx 5et7Noujvwss+h+/ZrY42/SG3eLyrjlsFjPO72Oy6Pr5k81i7ZG77A5cHn+fX2fxWLxpP5vH plWdbB73u48zefRtWcXo8XmTXABbFJdNSmpOZllqkb5dAlfG6sdKBXuEK+4ebmdtYDzB38XI ySEhYCIx69UvFghbTOLCvfVsXYxcHEICSxklFr2YyATh9DFJdB+czQpSxSagKfF38002EFtE QFXic9sCdpAiZoGdTBKnPq1nAkkIC4RKzOu7xQxiswAVrf25DizOK+AssXD/LnaIdXISJ49N BhvKKeAiMe/pY6AzOIC2OUvMPFUxgZF3ASPDKkbR1NLkguKk9FwjveLE3OLSvHS95PzcTYyQ 0Pu6g3HpMatDjAIcjEo8vDe8LocIsSaWFVfmHmKU4GBWEuHdAhLiTUmsrEotyo8vKs1JLT7E yMTBKdXAyHXjQJkc63fuhnKpR00X4wMM1rDzZet1CEcHLSw4x9K3fdXZ8vd5ibJs878dFJ5c +qHu6v3zC2ZHOmz4+eBR/zTnTUo7Yo7/msj0qrTn/GKvNaLzYx4eN21dxR5nmcV3OJjdRVxz wuryMjXOQJuGRYf6uVyFD4bJ7b19R8Iw9OR/Tz7GD3ZHlViKMxINtZiLihMB0YrsnxsCAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Since Exynos5420 there are async-bridges (ASB) between different IPs. These bridges must be operational during power domain on/off, ie. clocks used by these bridges should be enabled. This patch enabled these clocks during domain on/off. Signed-off-by: Andrzej Hajda Reviewed-by: Sylwester Nawrocki --- arch/arm/mach-exynos/pm_domains.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 0e2bc36..ecff522 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -37,6 +37,7 @@ struct exynos_pm_domain { struct clk *oscclk; struct clk *clk[MAX_CLK_PER_DOMAIN]; struct clk *pclk[MAX_CLK_PER_DOMAIN]; + struct clk *asb_clk[MAX_CLK_PER_DOMAIN]; }; static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) @@ -45,14 +46,19 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) void __iomem *base; u32 timeout, pwr; char *op; + int i; pd = container_of(domain, struct exynos_pm_domain, pd); base = pd->base; + for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { + if (IS_ERR(pd->asb_clk[i])) + break; + clk_prepare_enable(pd->asb_clk[i]); + } + /* Set oscclk before powering off a domain*/ if (!power_on) { - int i; - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { if (IS_ERR(pd->clk[i])) break; @@ -81,8 +87,6 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) /* Restore clocks after powering on a domain*/ if (power_on) { - int i; - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { if (IS_ERR(pd->clk[i])) break; @@ -92,6 +96,12 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) } } + for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { + if (IS_ERR(pd->asb_clk[i])) + break; + clk_disable_unprepare(pd->asb_clk[i]); + } + return 0; } @@ -137,6 +147,15 @@ static __init int exynos4_pm_init_power_domain(void) pd->pd.power_off = exynos_pd_power_off; pd->pd.power_on = exynos_pd_power_on; + for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { + char clk_name[8]; + + snprintf(clk_name, sizeof(clk_name), "asb%d", i); + pd->asb_clk[i] = clk_get(dev, clk_name); + if (IS_ERR(pd->asb_clk[i])) + break; + } + pd->oscclk = clk_get(dev, "oscclk"); if (IS_ERR(pd->oscclk)) goto no_clk;