From patchwork Thu Feb 5 12:35:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 5784301 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 40F7B9F302 for ; Thu, 5 Feb 2015 12:36:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 85E9B2026F for ; Thu, 5 Feb 2015 12:36:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E78F320268 for ; Thu, 5 Feb 2015 12:36:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757053AbbBEMgV (ORCPT ); Thu, 5 Feb 2015 07:36:21 -0500 Received: from mailout3.w1.samsung.com ([210.118.77.13]:9051 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757390AbbBEMgR (ORCPT ); Thu, 5 Feb 2015 07:36:17 -0500 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NJA00MC5TV7RV60@mailout3.w1.samsung.com>; Thu, 05 Feb 2015 12:40:19 +0000 (GMT) X-AuditID: cbfec7f5-b7fc86d0000066b7-d6-54d3632c5878 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 18.58.26295.C2363D45; Thu, 05 Feb 2015 12:33:48 +0000 (GMT) Received: from AMDC1061.digital.local ([106.116.147.88]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0NJA00AIBTO3X990@eusync2.samsung.com>; Thu, 05 Feb 2015 12:36:14 +0000 (GMT) From: Andrzej Hajda To: linux-samsung-soc@vger.kernel.org Cc: Andrzej Hajda , Marek Szyprowski , Kyungmin Park , Kukjin Kim , javier.martinez@collabora.co.uk, Liquid.Acid@gmx.net, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [RFC PATCH 3/3] ARM: dts: exynos5420: add async-bridge clock to disp1 power domain Date: Thu, 05 Feb 2015 13:35:39 +0100 Message-id: <1423139739-19881-4-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1423139739-19881-1-git-send-email-a.hajda@samsung.com> References: <1423139739-19881-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpnluLIzCtJLcpLzFFi42I5/e/4FV2d5MshBt/uyFncWneO1WL+ESBx 5et7Noujvwss+h+/ZrY42/SG3eLyrjlsFjPO72Oy6Pr5k81i7ZG77A5cHn+fX2fxWLxpP5vH plWdbB73u48zefRtWcXo8XmTXABbFJdNSmpOZllqkb5dAlfG95MXmQuesld8/7SBpYFxOVsX IyeHhICJxNlHk6FsMYkL99YD2VwcQgJLGSX2bNzFDOH0MUn8+76FHaSKTUBT4u/mm2AdIgKq Ep/bFrCDFDEL7GSSOPVpPVMXIweHsECsxJ9LtSAmC1DNhWuRIOW8As4Ssw53M0Isk5M4eWwy K4jNKeAiMe/pYxaQciGgmpmnKiYw8i5gZFjFKJpamlxQnJSea6RXnJhbXJqXrpecn7uJERJ4 X3cwLj1mdYhRgINRiYf3htflECHWxLLiytxDjBIczEoivFtAQrwpiZVVqUX58UWlOanFhxiZ ODilGhiLl+fKXS39vjzN4UYhDz+jarjmGvFXn1ZtMqtw9X6xcNHL+IBT4Xd8b1z7+mwWY/QK 1+LPR/f/+6EtvNs2cGWBQIDFxIoTnY32erOPi3pOrpnXmXyrcv7hY69e3NYTcr9oaSn3Rj/J v+ff5Zu9AT4bzlwpP7A9R2iW+lc5/QUXWGZ2TmpbGrtciaU4I9FQi7moOBEAdWlg3BoCAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP disp1 power domain requires operational async-bridge associated with HDMI, ie its clock should be enabled during power on/off. This patch fixes broken Odroid XU3 HDMI support. Signed-off-by: Andrzej Hajda --- arch/arm/boot/dts/exynos5420.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index b8f1c9f..13191fe 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -285,9 +285,11 @@ <&clock CLK_MOUT_SW_ACLK300>, <&clock CLK_MOUT_USER_ACLK300_DISP1>, <&clock CLK_MOUT_SW_ACLK400>, - <&clock CLK_MOUT_USER_ACLK400_DISP1>; + <&clock CLK_MOUT_USER_ACLK400_DISP1>, + <&clock CLK_HDMI>; clock-names = "oscclk", "pclk0", "clk0", - "pclk1", "clk1", "pclk2", "clk2"; + "pclk1", "clk1", "pclk2", "clk2", + "asb0"; }; pinctrl_0: pinctrl@13400000 {