From patchwork Wed Mar 18 03:08:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 6036081 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2D75DBF90F for ; Wed, 18 Mar 2015 03:04:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3DDEF204E3 for ; Wed, 18 Mar 2015 03:04:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 51B8D204EC for ; Wed, 18 Mar 2015 03:04:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754622AbbCRDEq (ORCPT ); Tue, 17 Mar 2015 23:04:46 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:29361 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754255AbbCRDEp (ORCPT ); Tue, 17 Mar 2015 23:04:45 -0400 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NLE001DC0JUGK50@mailout1.samsung.com>; Wed, 18 Mar 2015 12:04:42 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.50]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 6E.F3.17016.A4BE8055; Wed, 18 Mar 2015 12:04:42 +0900 (KST) X-AuditID: cbfee68d-f79296d000004278-6c-5508eb4a0059 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 09.1E.20081.A4BE8055; Wed, 18 Mar 2015 12:04:42 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NLE00A3M0JL1RL0@mmp2.samsung.com>; Wed, 18 Mar 2015 12:04:42 +0900 (KST) From: Alim Akhtar To: kgene@kernel.org Cc: linux-mmc@vger.kernel.org, ulf.hansson@linaro.org, jh80.chung@samsung.com, tgih.jun@samsung.com, dianders@chromium.org, alim.akhtar@gmail.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, a.kesavan@samsung.com, alim.akhtar@samsung.com Subject: [PATCH v6] ARM: dts: Add HS400 support for exynos5420 and exynos5800 Date: Wed, 18 Mar 2015 08:38:38 +0530 Message-id: <1426648118-20790-1-git-send-email-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.2.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRmVeSWpSXmKPExsVy+t8zI12v1xyhBrOnCVk8XrOYyWLprWqL B/O2sVnMP3KO1eLssoNsFjd+tbFa9D9+zWyx6fE1Vosj//sZLWac38dk8eH+RWaL42vDHXg8 ZjdcZPHYOesuu8emVZ1sHneu7WHz2Lyk3qNvyypGj8+b5ALYo7hsUlJzMstSi/TtErgyLuw6 yFTwU6bi+/OdbA2MByS6GDk5JARMJH7/7mWCsMUkLtxbz9bFyMUhJLCMUWLDu5ksMEXr5x5j A7GFBKYzSrycVQZhT2CSOPi5FsRmE9CWuDt9C9AgDg4RARGJ2Re4QOYwC6xjktiwaTfYAmEB X4k/Mw+CzWQRUJVY1HIcLM4r4C7x7/1URohdchJbbj1iB2mWEFjHLnHl+A0miAYBiW+TD7GA LJAQkJXYdIAZol5S4uCKGywTGAUXMDKsYhRNLUguKE5KLzLUK07MLS7NS9dLzs/dxAgJ+t4d jLcPWB9iFOBgVOLhlbjKESrEmlhWXJl7iNEUaMNEZinR5HxgbOWVxBsamxlZmJqYGhuZW5op ifMqSv0MFhJITyxJzU5NLUgtii8qzUktPsTIxMEp1cDorakk+2TOnNOlb4P+Lb605/wkK2fu Za+W3rxi4yaWsOhTmdc9h7CWamexTek+tpE3uIrqsti5PSf8LDuexClf2rsjfcXGvtySeUH3 bbe5l1WefXg83EGH56TRZZmdjxLze9Jv+LztLKmaszrxfCLflfKX1jFvg8y1/LVfHU7dODPD +VzrZl8lluKMREMt5qLiRACrIDjkdQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrDIsWRmVeSWpSXmKPExsVy+t9jQV2v1xyhBk9uc1k8XrOYyWLprWqL B/O2sVnMP3KO1eLssoNsFjd+tbFa9D9+zWyx6fE1Vosj//sZLWac38dk8eH+RWaL42vDHXg8 ZjdcZPHYOesuu8emVZ1sHneu7WHz2Lyk3qNvyypGj8+b5ALYoxoYbTJSE1NSixRS85LzUzLz 0m2VvIPjneNNzQwMdQ0tLcyVFPISc1NtlVx8AnTdMnOA7lRSKEvMKQUKBSQWFyvp22GaEBri pmsB0xih6xsSBNdjZIAGEtYxZlzYdZCp4KdMxffnO9kaGA9IdDFyckgImEisn3uMDcIWk7hw bz2YLSQwnVHi5awyCHsCk8TBz7UgNpuAtsTd6VuYuhg5OEQERCRmX+DqYuTiYBZYxySxYdNu JpAaYQFfiT8zD7KA2CwCqhKLWo6DxXkF3CX+vZ/KCLFLTmLLrUfsExi5FzAyrGIUTS1ILihO Ss811CtOzC0uzUvXS87P3cQIjqlnUjsYVzZYHGIU4GBU4uGVuMoRKsSaWFZcmXuIUYKDWUmE V6sFKMSbklhZlVqUH19UmpNafIjRFGj7RGYp0eR8YLznlcQbGpuYGVkamVkYmZibK4nzKtm3 hQgJpCeWpGanphakFsH0MXFwSjUwJhZEloXE/+vwWb9V89xGP01Lkx3x86yKmc+vW5Jdl/I6 3+Cfe/zTLyun/ZNbfKl3yi/jhIu2J5VebkuZb6hoGnI+W119OstH124H3QTtn/Xm7oomUzfL e3iYTv9016XdZwXH/XMtc700vPW/TWm4lxZ2IiBjK0dRY/Cm9JR8+6KVS/lqmy8osRRnJBpq MRcVJwIA2gqTRb8CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Seungwon Jeon HS400 timing values are added for SMDK5420, exynos5420-peach-pit and exynos5800-peach-pi boards. This also adds RCLK GPIO line, this gpio should be in pull-down state. This also enables HS400 on peach-pi and this updates the clock frequency to 800MHz to be set as input clock to controller. Signed-off-by: Seungwon Jeon Signed-off-by: Alim Akhtar [Alim: addressed review comments] Acked-by: Jaehoon Chung --- Changes in V6: Rebased on kukjin's for-next branch[0] (commit: 77105c8 Merge branch 'v4.0-samsung-fixes-2' into for-next) [0]: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +++- arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 7 +++++++ arch/arm/boot/dts/exynos5420-smdk5420.dts | 4 +++- arch/arm/boot/dts/exynos5800-peach-pi.dts | 7 +++++-- 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index d0ee55f..e158861 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -695,8 +695,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; }; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index ba686e4..8b15316 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -201,6 +201,13 @@ samsung,pin-drv = <3>; }; + sd0_rclk: sd0-rclk { + samsung,pins = "gpc0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + sd1_cmd: sd1-cmd { samsung,pins = "gpc1-1"; samsung,pin-function = <2>; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 7a56852..de5e41e 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -80,8 +80,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; cap-mmc-highspeed; }; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 7ea1d66..2e84613 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -650,15 +650,18 @@ num-slots = <1>; broken-cd; mmc-hs200-1_8v; + mmc-hs400-1_8v; cap-mmc-highspeed; non-removable; card-detect-delay = <200>; - clock-frequency = <400000000>; + clock-frequency = <800000000>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; };