From patchwork Wed Mar 18 15:52:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 6041271 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 54850BF90F for ; Wed, 18 Mar 2015 15:54:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 399B120450 for ; Wed, 18 Mar 2015 15:54:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 60E632044C for ; Wed, 18 Mar 2015 15:54:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755580AbbCRPyC (ORCPT ); Wed, 18 Mar 2015 11:54:02 -0400 Received: from mail-lb0-f177.google.com ([209.85.217.177]:36743 "EHLO mail-lb0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755095AbbCRPx6 (ORCPT ); Wed, 18 Mar 2015 11:53:58 -0400 Received: by lbblx11 with SMTP id lx11so10763278lbb.3; Wed, 18 Mar 2015 08:53:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=ERcwOvXd3btVhaEvXNTO6ZJVYmavtQf8XLm9/3gORkU=; b=Bwin+e56ZIgVCK3Xj9kl5EEvqmW0e29aHcJBnd1aixiZNFrNchd8hy7R/QJhWlVPhg q3GwkO3pQ6TCKxgWMXuHEr/v3busQyUik4FIx2CeeZGRWKTGNO+zLZDsQHaybmdKMc1c Y+oqMJBXPbdLxV4Dt1wHTaSFTcXaH8Lnw7RdULFs2qB9gXBitfKIkF8d7ileQgCn1YBv W+92hFdmjqy8bDMqe1CFEr2VqchdIeUlAfLKOiEmQXp7XeB5oWVw6+F+sAgcUU+osFLQ AByGH2J2Uj5eaAM4xkFk/J+0Er3VBH9Ncvdx+z4u00Pu5DGzgYJe4KacP+cixe+SBO9h Vmng== X-Received: by 10.152.21.99 with SMTP id u3mr64519798lae.105.1426694036369; Wed, 18 Mar 2015 08:53:56 -0700 (PDT) Received: from localhost.localdomain ([46.138.70.252]) by mx.google.com with ESMTPSA id zs4sm3458819lbb.48.2015.03.18.08.53.55 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Mar 2015 08:53:55 -0700 (PDT) From: Dmitry Osipenko To: digetx@gmail.com, Russell King , Kukjin Kim , Shawn Guo , Sascha Hauer , Joseph Lo , Stephen Warren , Peter De Schrijver , Thierry Reding Cc: linux-tegra@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3] ARM: l2c: Maintain CPU endianness for early resume function Date: Wed, 18 Mar 2015 18:52:44 +0300 Message-Id: <1426693972-6612-1-git-send-email-digetx@gmail.com> X-Mailer: git-send-email 2.3.2 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In big-endian CPU mode l2x0_saved_regs structure stores registers values in BE format. In order to maintain BE CPU mode, these values and immediate constants must be converted back to LE format before writing them to cache controller. Signed-off-by: Dmitry Osipenko Acked-by: Russell King --- Changelog: V2: no code change, fixed patch numbering, extended mail recipients list V3: added missed register reverse for 'ldr' instructions arch/arm/mm/l2c-l2x0-resume.S | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/mm/l2c-l2x0-resume.S b/arch/arm/mm/l2c-l2x0-resume.S index fda415e4..ecb5b74 100644 --- a/arch/arm/mm/l2c-l2x0-resume.S +++ b/arch/arm/mm/l2c-l2x0-resume.S @@ -30,9 +30,19 @@ ENTRY(l2c310_early_resume) teq r1, #0 reteq lr + @ Reverse for big-endian kernel +ARM_BE8(rev r2, r2) +ARM_BE8(rev r3, r3) +ARM_BE8(rev r4, r4) +ARM_BE8(rev r5, r5) +ARM_BE8(rev r6, r6) +ARM_BE8(rev r7, r7) +ARM_BE8(rev r8, r8) + @ The prefetch and power control registers are revision dependent @ and can be written whether or not the L2 cache is enabled ldr r0, [r1, #L2X0_CACHE_ID] +ARM_BE8(rev r0, r0) and r0, r0, #L2X0_CACHE_ID_RTL_MASK cmp r0, #L310_CACHE_ID_RTL_R2P0 strcs r7, [r1, #L310_PREFETCH_CTRL] @@ -41,6 +51,7 @@ ENTRY(l2c310_early_resume) @ Don't setup the L2 cache if it is already enabled ldr r0, [r1, #L2X0_CTRL] +ARM_BE8(rev r0, r0) tst r0, #L2X0_CTRL_EN retne lr @@ -51,6 +62,7 @@ ENTRY(l2c310_early_resume) str r2, [r1, #L2X0_AUX_CTRL] mov r9, #L2X0_CTRL_EN +ARM_BE8(rev r9, r9) str r9, [r1, #L2X0_CTRL] ret lr ENDPROC(l2c310_early_resume)