From patchwork Fri Mar 27 14:21:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Javier Martinez Canillas X-Patchwork-Id: 6107831 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4462EBF90F for ; Fri, 27 Mar 2015 14:22:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5C7572041B for ; Fri, 27 Mar 2015 14:22:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5D2EF203DF for ; Fri, 27 Mar 2015 14:22:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753167AbbC0OWM (ORCPT ); Fri, 27 Mar 2015 10:22:12 -0400 Received: from bhuna.collabora.co.uk ([93.93.135.160]:39388 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753091AbbC0OVy (ORCPT ); Fri, 27 Mar 2015 10:21:54 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: javier) with ESMTPSA id 4583D600E78 From: Javier Martinez Canillas To: Kukjin Kim Cc: Doug Anderson , Olof Johansson , Krzysztof Kozlowski , Abhilash Kesavan , Kevin Hilman , Tyler Baker , Steve Capper , Amit Kucheria , linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Javier Martinez Canillas Subject: [RFC PATCH 2/2] ARM: EXYNOS: Make sure that the Exynos5420 MDMA0 clock is enabled during suspend Date: Fri, 27 Mar 2015 15:21:37 +0100 Message-Id: <1427466097-7287-3-git-send-email-javier.martinez@collabora.co.uk> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1427466097-7287-1-git-send-email-javier.martinez@collabora.co.uk> References: <1427466097-7287-1-git-send-email-javier.martinez@collabora.co.uk> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit ae43b3289186 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12") added pm support for the pl330 dma driver but it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated during suspend and this clock needs to remain enabled in order to make the system resume from a system suspend state. To make sure that the clock is enabled during suspend, enable it prior to entering a suspend state and disable it once the system has resumed. Thanks to Abhilash Kesavan for figuring out that this was the issue. Fixes: ae43b32 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12") Signed-off-by: Javier Martinez Canillas --- arch/arm/mach-exynos/suspend.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index 1521eaf99265..6dbc0a6d1bb5 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -79,6 +80,7 @@ static const struct exynos_pm_data *pm_data; static int exynos5420_cpu_state; static unsigned int exynos_pmu_spare3; +static struct clk *clk; /* * GIC wake-up support @@ -374,6 +376,16 @@ static void exynos5420_pm_prepare(void) { unsigned int tmp; + /* + * Exynos5420 requires the MDMA0 controller clock to be + * ungated on suspend in order to be resumed correctly. + */ + clk = clk_get(NULL, "mdma0"); + if (IS_ERR(clk)) + pr_warn("Failed to get mdma0 clk (%ld)\n", PTR_ERR(clk)); + else + clk_prepare_enable(clk); + /* Set wake-up mask registers */ exynos_pm_set_wakeup_mask(); @@ -516,6 +528,9 @@ static void exynos5420_pm_resume(void) { unsigned long tmp; + if (!IS_ERR_OR_NULL(clk)) + clk_disable_unprepare(clk); + /* Restore the CPU0 low power state register */ tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG); pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,