From patchwork Mon Mar 30 15:53:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Javier Martinez Canillas X-Patchwork-Id: 6122561 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 426DC9F2EC for ; Mon, 30 Mar 2015 15:54:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 55EF32035B for ; Mon, 30 Mar 2015 15:54:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 688C22034F for ; Mon, 30 Mar 2015 15:54:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753150AbbC3Px6 (ORCPT ); Mon, 30 Mar 2015 11:53:58 -0400 Received: from bhuna.collabora.co.uk ([93.93.135.160]:43203 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752936AbbC3Pxl (ORCPT ); Mon, 30 Mar 2015 11:53:41 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: javier) with ESMTPSA id F207B600E79 From: Javier Martinez Canillas To: Stephen Boyd Cc: Mike Turquette , Sylwester Nawrocki , Tomasz Figa , Kukjin Kim , Olof Johansson , Doug Anderson , Krzysztof Kozlowski , Kevin Hilman , Tyler Baker , Abhilash Kesavan , Chanwoo Choi , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Javier Martinez Canillas Subject: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is enabled during suspend Date: Mon, 30 Mar 2015 17:53:22 +0200 Message-Id: <1427730803-28635-3-git-send-email-javier.martinez@collabora.co.uk> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1427730803-28635-1-git-send-email-javier.martinez@collabora.co.uk> References: <1427730803-28635-1-git-send-email-javier.martinez@collabora.co.uk> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit ae43b3289186 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12") added pm support for the pl330 dma driver but it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated during suspend and this clock needs to remain enabled in order to make the system resume from a system suspend state. To make sure that the clock is enabled during suspend, enable it prior to entering a suspend state and disable it once the system has resumed. Thanks to Abhilash Kesavan for figuring out that this was the issue. Fixes: ae43b32 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12") Signed-off-by: Javier Martinez Canillas --- drivers/clk/samsung/clk-exynos5420.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 07d666cc6a29..2d39b629144a 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -151,6 +151,7 @@ enum exynos5x_plls { static void __iomem *reg_base; static enum exynos5x_soc exynos5x_soc; +struct samsung_clk_provider *ctx; #ifdef CONFIG_PM_SLEEP static struct samsung_clk_reg_dump *exynos5x_save; @@ -275,8 +276,18 @@ static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, }; +/* + * list of clocks that have to be kept enabled during suspend/resume cycle. + */ +static unsigned int exynos5x_clk_suspend[] = { + CLK_MDMA0, +}; + static int exynos5420_clk_suspend(void) { + int i; + struct clk *clk; + samsung_clk_save(reg_base, exynos5x_save, ARRAY_SIZE(exynos5x_clk_regs)); @@ -287,11 +298,24 @@ static int exynos5420_clk_suspend(void) samsung_clk_restore(reg_base, exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); + for (i = 0; i < ARRAY_SIZE(exynos5x_clk_suspend); i++) { + clk = samsung_clk_lookup(ctx, exynos5x_clk_suspend[i]); + clk_prepare_enable(clk); + } + return 0; } static void exynos5420_clk_resume(void) { + int i; + struct clk *clk; + + for (i = 0; i < ARRAY_SIZE(exynos5x_clk_suspend); i++) { + clk = samsung_clk_lookup(ctx, exynos5x_clk_suspend[i]); + clk_disable_unprepare(clk); + } + samsung_clk_restore(reg_base, exynos5x_save, ARRAY_SIZE(exynos5x_clk_regs)); @@ -1255,8 +1279,6 @@ static const struct of_device_id ext_clk_match[] __initconst = { static void __init exynos5x_clk_init(struct device_node *np, enum exynos5x_soc soc) { - struct samsung_clk_provider *ctx; - if (np) { reg_base = of_iomap(np, 0); if (!reg_base)